Add RAS EEPROM table and I2C driver implementation.

Submitted by Andrey Grodzovsky on Aug. 21, 2019, 8:01 p.m.

Details

Reviewer None
Submitted Aug. 21, 2019, 8:01 p.m.
Last Updated Aug. 23, 2019, 2:47 a.m.
Revision 4

Cover Letter(s)

Revision 1
      This patch set introduces EEPROM table to store RAS errors which rise
during run time so on next driver load those errors can be retrieved
and action taken on them (e.g. Reserve bad memory pages to disallow
their usage by the GPU).

First patch is HW independent EEPROM table manager while the next 3
are Vega 20 specific I2C controller implementation to do the actual
EEPROM read/write over I2C.

Integration of this code into RAS will follow soon.

v2:
Add improved I2C controller TX buffer filling to avoid the slave
interpreting idle data line (SDA) as valid data.

v3:
Fix records store address calculation bug in EEPROM manager.
Fix bugs in I2C driver and revet the optimization from V2 as it's superfluous.
Remove the hack from SMU interface as the SMU found and fxied their bug.

v4:
Fix CRC calcualtion bug and address some style comments  from prevoius
review.

Andrey Grodzovsky (4):
  drm/amdgpu: Add RAS EEPROM table.
  drm/amd: Import smuio_11_0 headres for EEPROM access on Vega20
  drm/amd/powerplay: Add interface to lock SMU HW I2C.
  drm/amdgpu: Vega20 SMU I2C HW engine controller.

 drivers/gpu/drm/amd/amdgpu/Makefile                |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h            |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c     | 483 ++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h     |  90 +++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c         | 710 +++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h         |  34 +
 .../include/asic_reg/smuio/smuio_11_0_0_offset.h   |  92 +++
 .../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h  | 231 +++++++
 drivers/gpu/drm/amd/include/kgd_pp_interface.h     |   1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  16 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c |  19 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   1 +
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c   |   2 +-
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h   |   2 +
 14 files changed, 1687 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
    
Revision 2
      This patch set introduces EEPROM table to store RAS errors which rise
during run time so on next driver load those errors can be retrieved
and action taken on them (e.g. Reserve bad memory pages to disallow
their usage by the GPU).

First patch is HW independent EEPROM table manager while the next 3
are Vega 20 specific I2C controller implementation to do the actual
EEPROM read/write over I2C.

Integration of this code into RAS will follow soon.

v2:
Add improved I2C controller TX buffer filling to avoid the slave
interpreting idle data line (SDA) as valid data.

v3:
Fix records store address calculation bug in EEPROM manager.
Fix bugs in I2C driver and revet the optimization from V2 as it's superfluous.
Remove the hack from SMU interface as the SMU found and fxied their bug.

v4:
Fix CRC calcualtion bug and address some style comments  from prevoius
review.

Andrey Grodzovsky (4):
  drm/amdgpu: Add RAS EEPROM table.
  drm/amd: Import smuio_11_0 headres for EEPROM access on Vega20
  drm/amd/powerplay: Add interface to lock SMU HW I2C.
  drm/amdgpu: Vega20 SMU I2C HW engine controller.

 drivers/gpu/drm/amd/amdgpu/Makefile                |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h            |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c     | 483 ++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h     |  90 +++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c         | 710 +++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h         |  34 +
 .../include/asic_reg/smuio/smuio_11_0_0_offset.h   |  92 +++
 .../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h  | 231 +++++++
 drivers/gpu/drm/amd/include/kgd_pp_interface.h     |   1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  16 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c |  19 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   1 +
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c   |   2 +-
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h   |   2 +
 14 files changed, 1687 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
    
Revision 3
      This patch set introduces EEPROM table to store RAS errors which rise
during run time so on next driver load those errors can be retrieved
and action taken on them (e.g. Reserve bad memory pages to disallow
their usage by the GPU).

First patch is HW independent EEPROM table manager while the next 3
are Vega 20 specific I2C controller implementation to do the actual
EEPROM read/write over I2C.

Integration of this code into RAS will follow soon.

v2:
Add improved I2C controller TX buffer filling to avoid the slave
interpreting idle data line (SDA) as valid data.

v3:
Fix records store address calculation bug in EEPROM manager.
Fix bugs in I2C driver and revet the optimization from V2 as it's superfluous.
Remove the hack from SMU interface as the SMU found and fxied their bug.

v4:
Fix CRC calcualtion bug and address some style comments  from prevoius
review.

Andrey Grodzovsky (4):
  drm/amdgpu: Add RAS EEPROM table.
  drm/amd: Import smuio_11_0 headres for EEPROM access on Vega20
  drm/amd/powerplay: Add interface to lock SMU HW I2C.
  drm/amdgpu: Vega20 SMU I2C HW engine controller.

 drivers/gpu/drm/amd/amdgpu/Makefile                |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h            |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c     | 483 ++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h     |  90 +++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c         | 710 +++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h         |  34 +
 .../include/asic_reg/smuio/smuio_11_0_0_offset.h   |  92 +++
 .../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h  | 231 +++++++
 drivers/gpu/drm/amd/include/kgd_pp_interface.h     |   1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  16 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c |  19 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   1 +
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c   |   2 +-
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h   |   2 +
 14 files changed, 1687 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
    
Revision 4
      This patch set introduces EEPROM table to store RAS errors which rise
during run time so on next driver load those errors can be retrieved
and action taken on them (e.g. Reserve bad memory pages to disallow
their usage by the GPU).

First patch is HW independent EEPROM table manager while the next 3
are Vega 20 specific I2C controller implementation to do the actual
EEPROM read/write over I2C.

Integration of this code into RAS will follow soon.

v2:
Add improved I2C controller TX buffer filling to avoid the slave
interpreting idle data line (SDA) as valid data.

v3:
Fix records store address calculation bug in EEPROM manager.
Fix bugs in I2C driver and revet the optimization from V2 as it's superfluous.
Remove the hack from SMU interface as the SMU found and fxied their bug.

v4:
Fix CRC calcualtion bug and address some style comments  from prevoius
review.

Andrey Grodzovsky (4):
  drm/amdgpu: Add RAS EEPROM table.
  drm/amd: Import smuio_11_0 headres for EEPROM access on Vega20
  drm/amd/powerplay: Add interface to lock SMU HW I2C.
  drm/amdgpu: Vega20 SMU I2C HW engine controller.

 drivers/gpu/drm/amd/amdgpu/Makefile                |   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h            |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c     | 483 ++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h     |  90 +++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c         | 710 +++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h         |  34 +
 .../include/asic_reg/smuio/smuio_11_0_0_offset.h   |  92 +++
 .../include/asic_reg/smuio/smuio_11_0_0_sh_mask.h  | 231 +++++++
 drivers/gpu/drm/amd/include/kgd_pp_interface.h     |   1 +
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |  16 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c |  19 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   1 +
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c   |   2 +-
 .../gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h   |   2 +
 14 files changed, 1687 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
 create mode 100644 drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
    

Revisions