Tiger Lake batch 3

Submitted by José Roberto de Souza on Aug. 16, 2019, 8:04 a.m.

Details

Reviewer None
Submitted Aug. 16, 2019, 8:04 a.m.
Last Updated Aug. 24, 2019, 11:50 a.m.
Revision 5

Cover Letter(s)

Revision 1
      After switching to smaller series and getting the patches applied, it's
time to go with a bigger series again to get a bigger context of patches
coming. If needed I can split the series or delegate to the original
author to handle the reviews.

This should also give a warning-free driver load, so we can get CI up
and running. I ended up changing the patches and reordering them after I
didn't have the machine anymore, so I couldn't test the final state. But
I can do it soon.

I grouped the patches by context to make it easier to move them
around.

Batch 3 contains:

  - DDIC is gone

  - PSR: some of these patches are already in other series, but I needed
    them here in order to solve dependencies. They can continue their
    review either here or in the other series José sent.

    After reviewing some of these patches before sending, my feeling
    is that they could use some squashing: we add per-transcoder-psr to
    later restrict it. Just having the register in the transcoder is
    more a sign of encapsulation than that we really allow them on any
    transcoder.  I know that some of these patches were sent before we
    even have Tiger Lake, but now that we do maybe we could refactor
    than to be more straight to the point. José, could you take a look
    on those?

  - Registers moving from DDI to transcoder (also the case for the PSR
    patches)

  - Workarounds

  - Register state context and Render Context.

    Daniele: I added a "HACK" to your commit since we need to double
    check the spec

  - DisplayPort training sequence

  - Private PAT

  - Perf support

  - Format modifier changes in Gen12


Daniele Ceraolo Spurio (3):
  HACK: drm/i915/tgl: Gen12 render context size
  drm/i915/tgl: add Gen12 default indirect ctx offset
  drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (17):
  drm/i915/psr: Make PSR registers relative to transcoders
  drm/i915: Add transcoder restriction to PSR2
  drm/i915: Do not unmask PSR interruption in IRQ postinstall
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915/tgl: Change PSR2 transcoder restriction
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lionel Landwerlin (2):
  drm/i915/perf: add a parameter to control the size of OA buffer
  drm/i915/tgl: Add perf support on TGL

Lucas De Marchi (4):
  drm/i915/tgl: do not use DDIC
  drm/i915/tgl: Introduce initial Tiger Lake workarounds
  drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (8):
  drm/i915/tgl: Implement Wa_1406941453
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl: Report valid VDBoxes with SFC capability
  drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Updated Private PAT programming
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 193 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  | 108 +++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  21 ++
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 +++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 184 +++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 312 +++++++++-------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 161 ++++++---
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  31 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  36 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  18 +-
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  27 +-
 drivers/gpu/drm/i915/i915_irq.c               |  54 ++-
 drivers/gpu/drm/i915/i915_perf.c              | 337 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               | 202 +++++++++--
 drivers/gpu/drm/i915/intel_device_info.c      |   3 +-
 drivers/gpu/drm/i915/intel_pm.c               |  19 +-
 drivers/gpu/drm/i915/oa/i915_oa_tgl.c         | 113 ++++++
 drivers/gpu/drm/i915/oa/i915_oa_tgl.h         |  17 +
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 include/uapi/drm/i915_drm.h                   |   7 +
 32 files changed, 1733 insertions(+), 337 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
    
Revision 2
      v2 of https://patchwork.freedesktop.org/series/65290/

Differences from previous version:
  - Update patches that were already made available to their latest
    versions
  - Remove non-working W/A
  - Clean a little bit the PSR commits
  - Run checkpatch and fix warning
  - Add patch to update DMC so we don't keep getting flip_done timeout
  - Add hack to change powerwell that backs transcoders C and D.
  - Dropped nacked patch and replace with "drm/i915: Fix DP-MST crtc_mask".

Most of the pathes here can be reviewed as is, but we may need to split
the changes later for authors to take over on fixing commits.
There are some that are obviously not the final version. You can ignore
them but CI needs them to run successfully.

Daniele Ceraolo Spurio (4):
  HACK: drm/i915/tgl: Gen12 render context size
  drm/i915/tgl: add Gen12 default indirect ctx offset
  drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
  drm/i915/tgl: Gen12 csb support

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (16):
  drm/i915/tgl: Move transcoders to pipes' powerwells
  drm/i915/psr: Make PSR registers relative to transcoders
  drm/i915: Add transcoder restriction to PSR2
  drm/i915: Do not unmask PSR interruption in IRQ postinstall
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lionel Landwerlin (2):
  drm/i915/perf: add a parameter to control the size of OA buffer
  drm/i915/tgl: Add perf support on TGL

Lucas De Marchi (4):
  drm/i915/tgl: disable DDIC
  drm/i915/tgl: update DMC firmware to 2.04
  drm/i915/tgl: Introduce initial Tiger Lake workarounds
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (8):
  drm/i915/tgl: add support for reading the timestamp frequency
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl: Report valid VDBoxes with SFC capability
  rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Updated Private PAT programming
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

Ville Syrjälä (1):
  drm/i915: Fix DP-MST crtc_mask

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 193 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  | 108 +++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  20 ++
 .../drm/i915/display/intel_display_power.c    |   4 +-
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 +++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 181 +++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 308 +++++++++-------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 240 ++++++++++---
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  31 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  26 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  18 +-
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  26 +-
 drivers/gpu/drm/i915/i915_irq.c               |  54 ++-
 drivers/gpu/drm/i915/i915_perf.c              | 337 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               | 199 +++++++++--
 drivers/gpu/drm/i915/intel_csr.c              |   4 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   5 +-
 drivers/gpu/drm/i915/intel_pm.c               |  19 +-
 drivers/gpu/drm/i915/oa/i915_oa_tgl.c         | 112 ++++++
 drivers/gpu/drm/i915/oa/i915_oa_tgl.h         |  16 +
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 include/uapi/drm/i915_drm.h                   |   7 +
 35 files changed, 1796 insertions(+), 341 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
    
Revision 3
      v2 of https://patchwork.freedesktop.org/series/65290/

Differences from previous version:
  - Update patches that were already made available to their latest
    versions
  - Remove non-working W/A
  - Clean a little bit the PSR commits
  - Run checkpatch and fix warning
  - Add patch to update DMC so we don't keep getting flip_done timeout
  - Add hack to change powerwell that backs transcoders C and D.
  - Dropped nacked patch and replace with "drm/i915: Fix DP-MST crtc_mask".

Most of the pathes here can be reviewed as is, but we may need to split
the changes later for authors to take over on fixing commits.
There are some that are obviously not the final version. You can ignore
them but CI needs them to run successfully.

Daniele Ceraolo Spurio (4):
  HACK: drm/i915/tgl: Gen12 render context size
  drm/i915/tgl: add Gen12 default indirect ctx offset
  drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
  drm/i915/tgl: Gen12 csb support

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (16):
  drm/i915/tgl: Move transcoders to pipes' powerwells
  drm/i915/psr: Make PSR registers relative to transcoders
  drm/i915: Add transcoder restriction to PSR2
  drm/i915: Do not unmask PSR interruption in IRQ postinstall
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lionel Landwerlin (2):
  drm/i915/perf: add a parameter to control the size of OA buffer
  drm/i915/tgl: Add perf support on TGL

Lucas De Marchi (4):
  drm/i915/tgl: disable DDIC
  drm/i915/tgl: update DMC firmware to 2.04
  drm/i915/tgl: Introduce initial Tiger Lake workarounds
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (8):
  drm/i915/tgl: add support for reading the timestamp frequency
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl: Report valid VDBoxes with SFC capability
  rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Updated Private PAT programming
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

Ville Syrjälä (1):
  drm/i915: Fix DP-MST crtc_mask

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 193 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  | 108 +++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  20 ++
 .../drm/i915/display/intel_display_power.c    |   4 +-
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 +++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 181 +++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 308 +++++++++-------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 240 ++++++++++---
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  31 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  26 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  18 +-
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  26 +-
 drivers/gpu/drm/i915/i915_irq.c               |  54 ++-
 drivers/gpu/drm/i915/i915_perf.c              | 337 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               | 199 +++++++++--
 drivers/gpu/drm/i915/intel_csr.c              |   4 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   5 +-
 drivers/gpu/drm/i915/intel_pm.c               |  19 +-
 drivers/gpu/drm/i915/oa/i915_oa_tgl.c         | 112 ++++++
 drivers/gpu/drm/i915/oa/i915_oa_tgl.h         |  16 +
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 include/uapi/drm/i915_drm.h                   |   7 +
 35 files changed, 1796 insertions(+), 341 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
    
Revision 4
      v2 of https://patchwork.freedesktop.org/series/65290/

Differences from previous version:
  - Update patches that were already made available to their latest
    versions
  - Remove non-working W/A
  - Clean a little bit the PSR commits
  - Run checkpatch and fix warning
  - Add patch to update DMC so we don't keep getting flip_done timeout
  - Add hack to change powerwell that backs transcoders C and D.
  - Dropped nacked patch and replace with "drm/i915: Fix DP-MST crtc_mask".

Most of the pathes here can be reviewed as is, but we may need to split
the changes later for authors to take over on fixing commits.
There are some that are obviously not the final version. You can ignore
them but CI needs them to run successfully.

Daniele Ceraolo Spurio (4):
  HACK: drm/i915/tgl: Gen12 render context size
  drm/i915/tgl: add Gen12 default indirect ctx offset
  drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
  drm/i915/tgl: Gen12 csb support

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (16):
  drm/i915/tgl: Move transcoders to pipes' powerwells
  drm/i915/psr: Make PSR registers relative to transcoders
  drm/i915: Add transcoder restriction to PSR2
  drm/i915: Do not unmask PSR interruption in IRQ postinstall
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lionel Landwerlin (2):
  drm/i915/perf: add a parameter to control the size of OA buffer
  drm/i915/tgl: Add perf support on TGL

Lucas De Marchi (4):
  drm/i915/tgl: disable DDIC
  drm/i915/tgl: update DMC firmware to 2.04
  drm/i915/tgl: Introduce initial Tiger Lake workarounds
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (8):
  drm/i915/tgl: add support for reading the timestamp frequency
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl: Report valid VDBoxes with SFC capability
  rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Updated Private PAT programming
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

Ville Syrjälä (1):
  drm/i915: Fix DP-MST crtc_mask

 drivers/gpu/drm/i915/Makefile                 |   3 +-
 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 193 +++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  | 108 +++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  20 ++
 .../drm/i915/display/intel_display_power.c    |   4 +-
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 +++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 181 +++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 308 +++++++++-------
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++-
 drivers/gpu/drm/i915/gem/i915_gem_context.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 240 ++++++++++---
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  31 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  26 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  18 +-
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  26 +-
 drivers/gpu/drm/i915/i915_irq.c               |  54 ++-
 drivers/gpu/drm/i915/i915_perf.c              | 337 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h               | 199 +++++++++--
 drivers/gpu/drm/i915/intel_csr.c              |   4 +-
 drivers/gpu/drm/i915/intel_device_info.c      |   5 +-
 drivers/gpu/drm/i915/intel_pm.c               |  19 +-
 drivers/gpu/drm/i915/oa/i915_oa_tgl.c         | 112 ++++++
 drivers/gpu/drm/i915/oa/i915_oa_tgl.h         |  16 +
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 include/uapi/drm/i915_drm.h                   |   7 +
 35 files changed, 1796 insertions(+), 341 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.c
 create mode 100644 drivers/gpu/drm/i915/oa/i915_oa_tgl.h
    
Revision 5
      v3 of https://patchwork.freedesktop.org/series/65290/

Note that some patches were handled outside of the "batch series for
Tiger Lake". Compared to v2 several patches were merged. Anothe great
portion received comments and reviews. Unfortunately some people
commented/reviewed the wrong revision of the patch, making it difficult
to follow up on adding the R-b. Also, patchwork got pretty confused with
the patches sent by José to cover the review feedback. So, if I didn't
handle your comment, I will double check for the next version. If you
reviewed a patch and it does not show here, then please add your r-b
again.

2 patches to add perf support are dropped: one of them was missing
a userspace component and the other one depends on the first.

Patches that still need to handle the comments from previous versions
are prefixed with FIXME and are not meant to be merged.

For the patches that already have a r-b tag: I was planning to merge
them and remove from this series, but in the end I felt more confortable
doing it in steps: add them here again and merge them later.

Lucas De Marchi

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (12):
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  FIXME: drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lucas De Marchi (1):
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (5):
  drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  FIXME: drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 199 +++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  | 105 ++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  20 ++
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 ++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 179 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 200 +++++++++---------
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++++++-
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 156 ++++++++++----
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  30 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   3 +
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  10 +-
 drivers/gpu/drm/i915/i915_irq.c               |  52 ++++-
 drivers/gpu/drm/i915/i915_perf.c              |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  35 ++-
 drivers/gpu/drm/i915/intel_pm.c               |  18 +-
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 22 files changed, 1011 insertions(+), 209 deletions(-)
    

Revisions

Patches download mbox

# Name Submitter State A F R T
[01/39] drm/i915/tgl: do not use DDIC Lucas De Marchi New 1
[02/39] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi New
[03/39] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi New
[04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi New
[05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi New
[06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi New 1
[07/39] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi New
[08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi New
[09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi New
[10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi Accepted 1
[11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi New
[12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi Accepted
[13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi New
[14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi New 1
[15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi New
[16/39] drm/i915: Disable pipes in reverse order Lucas De Marchi Accepted
[17/39] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi New
[18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi New 1
[19/39] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi Accepted 3
[20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi New
[21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi Accepted
[22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Lucas De Marchi New
[23/39] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi New 1
[24/39] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi New
[25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi New
[26/39] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi Accepted
[27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi New 1
[28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi New
[29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi New
[30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi New
[31/39] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi Accepted
[32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi Accepted 1
[33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi New 1
[34/39] drm/i915/tgl: Add perf support on TGL Lucas De Marchi New
[35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi New
[36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi New
[37/39] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi New
[38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi New
[39/39] drm/i915/tgl: Gen-12 media compression Lucas De Marchi New

Tests

CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14046
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/

Known issues
------------

  Here are the changes found in Patchwork_14046 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u3/igt@debugfs_test@read_all_entries.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][3] -> [INCOMPLETE][4] ([fdo#107718])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_busy@basic-flip-a:
    - fi-kbl-7567u:       [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html

  
#### Possible fixes ####

  * igt@gem_exec_reloc@basic-write-gtt:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u3/igt@gem_exec_reloc@basic-write-gtt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u3/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][9] ([fdo#111108]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
    - fi-bwr-2160:        [DMESG-WARN][11] ([fdo#111115]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-bwr-2160/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        [DMESG-FAIL][13] ([fdo#111115]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html

  * igt@i915_selftest@live_requests:
    - fi-byt-j1900:       [INCOMPLETE][15] ([fdo#102657]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-byt-j1900/igt@i915_selftest@live_requests.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-byt-j1900/igt@i915_selftest@live_requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [DMESG-WARN][17] ([fdo#102505] / [fdo#110390]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
  [fdo#111115]: https://bugs.freedesktop.org/show_bug.cgi?id=111115


Participating hosts (54 -> 45)
------------------------------

  Additional (1): fi-cfl-8700k 
  Missing    (10): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6716 -> Patchwork_14046

  CI-20190529: 20190529
  CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14046: 5390f66e917426e5dc5c169cc45c04935ab9ca00 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5390f66e9174 drm/i915/tgl: Gen-12 media compression
ad1ee48f6561 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
94f0008b78ce drm/i915/tgl: Gen-12 render decompression
a8f121f6224c drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
ec3736e13a4b drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
cc1d225b2d89 drm/i915/tgl: Add perf support on TGL
812b8979deb4 drm/i915/perf: add a parameter to control the size of OA buffer
d07f569dbdfc drm/i915/tgl/perf: use the same oa ctx_id format as icl
f5852b6a5343 drm/i915/tgl: Updated Private PAT programming
9a45d563be0c drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
5fb45b0f331a drm/i915/tgl: Report valid VDBoxes with SFC capability
06ab10d9acec drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
6ffd68d96f23 drm/i915/tgl: add Gen12 default indirect ctx offset
02738cff2fc6 HACK: drm/i915/tgl: Gen12 render context size
9a5fcbcdce67 drm/i915/tgl: Implement TGL DisplayPort training sequence
19e7d157eeab drm/i915/tgl: move DP_TP_* to transcoder
df2f2dd03b35 drm/i915/tgl: Register state context definition for Gen12
9f588da30621 drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
71de6cdc0cfe drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
c9ba1d70c006 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
e0b3f8f95c79 drm/i915/tgl: Implement Wa_1406941453
646b03f0618a drm/i915/tgl: Introduce initial Tiger Lake workarounds
31a881d23902 drm/i915/tgl: Select master transcoder in DP MST
e4f1a7b7ac7d drm/i915: Disable pipes in reverse order
be1c98132963 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
a74e4acb4ff7 drm/i915: Add for_each_new_intel_connector_in_state()
3c79bc060462 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
09bfdb8f1220 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
6a5a43b3886e drm/i915/tgl: Access the right register when handling PSR interruptions
3e0a6b536020 drm/i915/tgl: PSR link standby is not supported anymore
d822292eb833 drm/i915: Do not read PSR2 register in transcoders without PSR2
83d401588ff1 drm/i915/tgl: Change PSR2 transcoder restriction
2b396b0fd3a0 drm/i915: Guard and warn if more than one eDP panel is present
451e5d5e655b drm/i915/bdw+: Enable PSR in any eDP port
d626b231f0fb drm/i915/psr: Only handle interruptions of the transcoder in use
39b89150c6cd drm/i915: Do not unmask PSR interruption in IRQ postinstall
7cfc49277b02 drm/i915: Add transcoder restriction to PSR2
c0c2c6e584ca drm/i915/psr: Make PSR registers relative to transcoders
2f6d4ad3eda1 drm/i915/tgl: do not use DDIC
$ dim checkpatch origin/drm-tip
2f6d4ad3eda1 drm/i915/tgl: do not use DDIC
c0c2c6e584ca drm/i915/psr: Make PSR registers relative to transcoders
-:427: WARNING:LONG_LINE_COMMENT: line over 100 characters
#427: FILE: drivers/gpu/drm/i915/i915_reg.h:4311:
+#define EDP_PSR_AUX_DATA(tran, i)		_MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */

total: 0 errors, 1 warnings, 0 checks, 393 lines checked
7cfc49277b02 drm/i915: Add transcoder restriction to PSR2
39b89150c6cd drm/i915: Do not unmask PSR interruption in IRQ postinstall
d626b231f0fb drm/i915/psr: Only handle interruptions of the transcoder in use
-:229: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#229: FILE: drivers/gpu/drm/i915/i915_reg.h:4292:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		(trans == TRANSCODER_EDP ? 0 : (trans + 1) * 8)

-:229: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'trans' may be better as '(trans)' to avoid precedence issues
#229: FILE: drivers/gpu/drm/i915/i915_reg.h:4292:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		(trans == TRANSCODER_EDP ? 0 : (trans + 1) * 8)

total: 0 errors, 0 warnings, 2 checks, 203 lines checked
451e5d5e655b drm/i915/bdw+: Enable PSR in any eDP port
-:28: ERROR:CODE_INDENT: code indent should use tabs where possible
#28: FILE: drivers/gpu/drm/i915/display/intel_psr.c:581:
+         * BDW+ platforms with DDI implementation of PSR have different$

total: 1 errors, 0 warnings, 0 checks, 14 lines checked
2b396b0fd3a0 drm/i915: Guard and warn if more than one eDP panel is present
83d401588ff1 drm/i915/tgl: Change PSR2 transcoder restriction
d822292eb833 drm/i915: Do not read PSR2 register in transcoders without PSR2
3e0a6b536020 drm/i915/tgl: PSR link standby is not supported anymore
6a5a43b3886e drm/i915/tgl: Access the right register when handling PSR interruptions
09bfdb8f1220 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
3c79bc060462 drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
a74e4acb4ff7 drm/i915: Add for_each_new_intel_connector_in_state()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:26: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+		for_each_if ((__state)->base.connectors[__i].ptr && \

-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \

-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

total: 1 errors, 3 warnings, 2 checks, 14 lines checked
be1c98132963 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:25: CHECK:LINE_SPACING: Please don't use multiple blank lines
#25: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
 
+

-:33: WARNING:LONG_LINE: line over 100 characters
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \

-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#33: FILE: drivers/gpu/drm/i915/display/intel_display.h:423:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

total: 0 errors, 1 warnings, 4 checks, 22 lines checked
e4f1a7b7ac7d drm/i915: Disable pipes in reverse order
31a881d23902 drm/i915/tgl: Select master transcoder in DP MST
646b03f0618a drm/i915/tgl: Introduce initial Tiger Lake workarounds
e0b3f8f95c79 drm/i915/tgl: Implement Wa_1406941453
c9ba1d70c006 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
71de6cdc0cfe drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
-:11: WARNING:BAD_SIGN_OFF: Duplicate signature
#11: 
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

total: 0 errors, 1 warnings, 0 checks, 8 lines checked
9f588da30621 drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
df2f2dd03b35 drm/i915/tgl: Register state context definition for Gen12
-:16: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#16: 
the gen8 path), fix length of first LRI for non-rcs to include the semaphore

total: 0 errors, 1 warnings, 0 checks, 240 lines checked
19e7d157eeab drm/i915/tgl: move DP_TP_* to transcoder
9a5fcbcdce67 drm/i915/tgl: Implement TGL DisplayPort training sequence
02738cff2fc6 HACK: drm/i915/tgl: Gen12 render context size
6ffd68d96f23 drm/i915/tgl: add Gen12 default indirect ctx offset
06ab10d9acec drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
5fb45b0f331a drm/i915/tgl: Report valid VDBoxes with SFC capability
9a45d563be0c drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
f5852b6a5343 drm/i915/tgl: Updated Private PAT programming
d07f569dbdfc drm/i915/tgl/perf: use the same oa ctx_id format as icl
812b8979deb4 drm/i915/perf: add a parameter to control the size of OA buffer
cc1d225b2d89 drm/i915/tgl: Add perf support on TGL
-:398: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#398: FILE: drivers/gpu/drm/i915/i915_perf.c:3880:
+			dev_priv->perf.gen8_valid_ctx_bit = (1<<16);
 			                                      ^

-:410: CHECK:LINE_SPACING: Please don't use multiple blank lines
#410: FILE: drivers/gpu/drm/i915/i915_reg.h:702:
 
+

-:552: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#552: 
new file mode 100644

-:557: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#557: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.c:1:
+/*

-:558: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#558: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.c:2:
+ * SPDX-License-Identifier: MIT

-:676: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#676: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.h:1:
+/*

-:677: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#677: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.h:2:
+ * SPDX-License-Identifier: MIT

-:690: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#690: FILE: drivers/gpu/drm/i915/oa/i915_oa_tgl.h:15:
+extern void i915_perf_load_test_config_tgl(struct drm_i915_private *dev_priv);

total: 0 errors, 5 warnings, 3 checks, 619 lines checked
ec3736e13a4b drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
a8f121f6224c drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
94f0008b78ce drm/i915/tgl: Gen-12 render decompression
-:134: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#134: FILE: drivers/gpu/drm/i915/display/intel_display.c:2712:
+				tile_width = 64/cpp;
 				               ^

total: 0 errors, 0 warnings, 1 checks, 203 lines checked
ad1ee48f6561 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
5390f66e9174 drm/i915/tgl: Gen-12 media compression
-:50: WARNING:TABSTOP: Statements should start on a tabstop
#50: FILE: drivers/gpu/drm/i915/display/intel_display.c:2271:
+	      return true;

-:53: WARNING:TABSTOP: Statements should start on a tabstop
#53: FILE: drivers/gpu/drm/i915/display/intel_display.c:2274:
+	      return color_plane == 1;

-:55: WARNING:TABSTOP: Statements should start on a tabstop
#55: FILE: drivers/gpu/drm/i915/display/intel_display.c:2276:
+	      return false;

-:72: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#72: FILE: drivers/gpu/drm/i915/display/intel_display.c:2539:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 4 warnings, 0 checks, 134 lines checked
CI Bug Log - changes from CI_DRM_6716_full -> Patchwork_14046_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14046_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-kbl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#103665])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_exec_schedule@pi-ringfull-bsd:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#111325]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb7/igt@gem_exec_schedule@pi-ringfull-bsd.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@gem_exec_schedule@pi-ringfull-bsd.html

  * igt@i915_pm_rpm@fences:
    - shard-iclb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108840])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@i915_pm_rpm@fences.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@i915_pm_rpm@fences.html

  * igt@i915_selftest@live_hugepages:
    - shard-snb:          [PASS][7] -> [INCOMPLETE][8] ([fdo#105411])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-snb7/igt@i915_selftest@live_hugepages.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-snb6/igt@i915_selftest@live_hugepages.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#103232]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-skl:          [PASS][11] -> [INCOMPLETE][12] ([fdo#110741])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
    - shard-apl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([fdo#104873])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-kbl:          [PASS][17] -> [FAIL][18] ([fdo#100368])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl3/igt@kms_flip@plain-flip-fb-recreate.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167]) +5 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#108145])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145] / [fdo#110403])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb6/igt@kms_psr@psr2_no_drrs.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109276]) +14 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [SKIP][29] ([fdo#111325]) -> [PASS][30] +4 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb6/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][31] ([fdo#109276]) -> [PASS][32] +9 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_linear_blits@normal:
    - shard-iclb:         [INCOMPLETE][33] ([fdo#107713]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb7/igt@gem_linear_blits@normal.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@gem_linear_blits@normal.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +9 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-apl6/igt@i915_suspend@sysfs-reader.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-apl8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [FAIL][37] ([fdo#102670]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][39] ([fdo#105363]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][41] ([fdo#109507]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-kbl:          [DMESG-WARN][43] ([fdo#103313]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-iclb:         [FAIL][45] ([fdo#103167]) -> [PASS][46] +6 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-skl:          [FAIL][47] ([fdo#103167]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][49] ([fdo#108145]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][51] ([fdo#109642] / [fdo#111068]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@kms_psr2_su@page_flip.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_sprite_mmap_cpu:
    - shard-iclb:         [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][55] ([fdo#99912]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-apl1/igt@kms_setmode@basic.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-apl1/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-kbl:          [INCOMPLETE][57] ([fdo#103665]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-kbl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-kbl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [INCOMPLETE][59] ([fdo#104108]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-skl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-skl8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [FAIL][61] ([fdo#111330]) -> [SKIP][62] ([fdo#109276])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb3/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@gem_mocs_settings@mocs-reset-bsd2:
    - shard-iclb:         [SKIP][63] ([fdo#109276]) -> [FAIL][64] ([fdo#111330])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14046/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6716 -> Patchwork_14046

  CI-20190529: 20190529
  CI_DRM_6716: 64ecd8f88d7b55de82ff414784ae4daca93d0577 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14046: 5390f66e917426e5dc5c169cc45c04935ab9ca00 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: do not use DDIC
Okay!

Commit: drm/i915/psr: Make PSR registers relative to transcoders
Okay!

Commit: drm/i915: Add transcoder restriction to PSR2
Okay!

Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!

Commit: drm/i915/tgl: Change PSR2 transcoder restriction
Okay!

Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2
Okay!

Commit: drm/i915/tgl: PSR link standby is not supported anymore
Okay!

Commit: drm/i915/tgl: Access the right register when handling PSR interruptions
Okay!

Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Okay!

Commit: drm/i915/mst: Do not hardcoded the crtcs that encoder can connect
Okay!

Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!

Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Okay!

Commit: drm/i915: Disable pipes in reverse order
Okay!

Commit: drm/i915/tgl: Select master transcoder in DP MST
Okay!

Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Okay!

Commit: drm/i915/tgl: Implement Wa_1406941453
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Okay!

Commit: drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads
Okay!

Commit: drm/i915/tgl: Register state context definition for Gen12
Okay!

Commit: drm/i915/tgl: move DP_TP_* to transcoder
Okay!

Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence
Okay!

Commit: HACK: drm/i915/tgl: Gen12 render context size
Okay!

Commit: drm/i915/tgl: add Gen12 default indirect ctx offset
Okay!

Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Okay!

Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability
Okay!

Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Updated Private PAT programming
Okay!

Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl
Okay!

Commit: drm/i915/perf: add a parameter to control the size of OA buffer
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216

Commit: drm/i915/tgl: Add perf support on TGL
Okay!

Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
Okay!

Patches download mbox

# Name Submitter State A F R T
[v2,01/40] drm/i915/tgl: disable DDIC Lucas De Marchi Accepted
[v2,02/40] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi Accepted 1
[v2,03/40] drm/i915/tgl: Move transcoders to pipes' powerwells Lucas De Marchi Accepted 1
[v2,04/40] drm/i915/tgl: update DMC firmware to 2.04 Lucas De Marchi Accepted 1
[v2,05/40] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi Superseded
[v2,06/40] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi Superseded
[v2,07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi Superseded
[v2,08/40] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi New
[v2,09/40] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi New
[v2,10/40] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi New
[v2,11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi New
[v2,12/40] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi New
[v2,13/40] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi New
[v2,14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi New
[v2,15/40] drm/i915: Fix DP-MST crtc_mask Lucas De Marchi New 1
[v2,16/40] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi New 1
[v2,17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi New 1
[v2,18/40] drm/i915: Disable pipes in reverse order Lucas De Marchi New 1
[v2,19/40] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi New 1
[v2,20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi New 1
[v2,21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi New 1
[v2,22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi New
[v2,23/40] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi New
[v2,24/40] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi New
[v2,25/40] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi New 1
[v2,26/40] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi New 1
[v2,27/40] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi New 1
[v2,28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi New 1
[v2,29/40] drm/i915/tgl: Gen12 csb support Lucas De Marchi New 1
[v2,30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi New 1
[v2,31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi New 1
[v2,32/40] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi New 1
[v2,33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi New
[v2,34/40] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi New
[v2,35/40] drm/i915/tgl: Add perf support on TGL Lucas De Marchi New
[v2,36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi New
[v2,37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi New 1
[v2,38/40] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi New
[v2,39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi New 1
[v2,40/40] drm/i915/tgl: Gen-12 media compression Lucas De Marchi New 1

Tests

CI Bug Log - changes from CI_DRM_6725 -> Patchwork_14069
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14069 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14069, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14069:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_sync@basic-store-each:
    - fi-cfl-8109u:       [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-cfl-8109u/igt@gem_sync@basic-store-each.html

  
Known issues
------------

  Here are the changes found in Patchwork_14069 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@gem_flink_basic@flink-lifetime:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#107724]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u3/igt@gem_flink_basic@flink-lifetime.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [PASS][7] -> [FAIL][8] ([fdo#103167])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@gem_linear_blits@basic:
    - fi-icl-u3:          [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u3/igt@gem_linear_blits@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u3/igt@gem_linear_blits@basic.html

  * igt@kms_busy@basic-flip-a:
    - fi-kbl-7567u:       [SKIP][11] ([fdo#109271] / [fdo#109278]) -> [PASS][12] +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-icl-u2:          [FAIL][13] ([fdo#109483] / [fdo#109635 ]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6725/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14069/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6725 -> Patchwork_14069

  CI-20190529: 20190529
  CI_DRM_6725: fdcbe4ab792e64f23631fcb6a9d58c2cf03d74f7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14069: 32fc1d4b22a3b512cfa2d1b5576888f49cad5c93 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

32fc1d4b22a3 drm/i915/tgl: Gen-12 media compression
523159de2114 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
4d432593e93d drm/i915/tgl: Gen-12 render decompression
ed7414e63958 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
722ded5b9285 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
6614f3d1a6f2 drm/i915/tgl: Add perf support on TGL
493819143bc7 drm/i915/perf: add a parameter to control the size of OA buffer
ea7621575fd9 drm/i915/tgl/perf: use the same oa ctx_id format as icl
240a129f0132 drm/i915/tgl: Updated Private PAT programming
623edef0032b rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
230eba25e017 drm/i915/tgl: Report valid VDBoxes with SFC capability
5453b392d597 drm/i915/tgl: Gen12 csb support
bde4c00b75c9 drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
bfbb493106a1 drm/i915/tgl: add Gen12 default indirect ctx offset
86de648919da HACK: drm/i915/tgl: Gen12 render context size
d0ca1f27b4a0 drm/i915/tgl: Implement TGL DisplayPort training sequence
df4c77de5dd1 drm/i915/tgl: move DP_TP_* to transcoder
94baf2b17b36 drm/i915/tgl: Register state context definition for Gen12
6cdda9b265af drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
c77dbff20a84 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
6a6b80f2fb18 drm/i915/tgl: Introduce initial Tiger Lake workarounds
08b6786f83a9 drm/i915/tgl: Select master transcoder in DP MST
e5990121b4b6 drm/i915: Disable pipes in reverse order
c29f6126d5bc drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
8a0acb1f6f18 drm/i915: Add for_each_new_intel_connector_in_state()
b20288b02d29 drm/i915: Fix DP-MST crtc_mask
06803b514364 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
0d7f5c32f219 drm/i915/tgl: Access the right register when handling PSR interruptions
b9911dff9e65 drm/i915/tgl: PSR link standby is not supported anymore
03270e92e574 drm/i915: Do not read PSR2 register in transcoders without PSR2
d2a1e84537f6 drm/i915: Guard and warn if more than one eDP panel is present
1470888c4e04 drm/i915/bdw+: Enable PSR in any eDP port
3647639077cd drm/i915/psr: Only handle interruptions of the transcoder in use
ea93386d65d2 drm/i915: Do not unmask PSR interruption in IRQ postinstall
66b0f8d14a5c drm/i915: Add transcoder restriction to PSR2
c7f6f41671dc drm/i915/psr: Make PSR registers relative to transcoders
6d8b64b06ed0 drm/i915/tgl: update DMC firmware to 2.04
bc67233266e2 drm/i915/tgl: Move transcoders to pipes' powerwells
90d92ce242b9 drm/i915/tgl: add support for reading the timestamp frequency
bfd5dba4649b drm/i915/tgl: disable DDIC
$ dim checkpatch origin/drm-tip
bfd5dba4649b drm/i915/tgl: disable DDIC
90d92ce242b9 drm/i915/tgl: add support for reading the timestamp frequency
bc67233266e2 drm/i915/tgl: Move transcoders to pipes' powerwells
6d8b64b06ed0 drm/i915/tgl: update DMC firmware to 2.04
c7f6f41671dc drm/i915/psr: Make PSR registers relative to transcoders
-:428: WARNING:LONG_LINE_COMMENT: line over 100 characters
#428: FILE: drivers/gpu/drm/i915/i915_reg.h:4246:
+#define EDP_PSR_AUX_DATA(tran, i)		_MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */

total: 0 errors, 1 warnings, 0 checks, 393 lines checked
66b0f8d14a5c drm/i915: Add transcoder restriction to PSR2
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
Since BDW PSR is allowed on any port, but we need to restrict by transcoder.

total: 0 errors, 1 warnings, 0 checks, 28 lines checked
ea93386d65d2 drm/i915: Do not unmask PSR interruption in IRQ postinstall
3647639077cd drm/i915/psr: Only handle interruptions of the transcoder in use
-:230: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#230: FILE: drivers/gpu/drm/i915/i915_reg.h:4227:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
+						 0 : ((trans) + 1) * 8)

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
1470888c4e04 drm/i915/bdw+: Enable PSR in any eDP port
d2a1e84537f6 drm/i915: Guard and warn if more than one eDP panel is present
03270e92e574 drm/i915: Do not read PSR2 register in transcoders without PSR2
b9911dff9e65 drm/i915/tgl: PSR link standby is not supported anymore
0d7f5c32f219 drm/i915/tgl: Access the right register when handling PSR interruptions
06803b514364 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
b20288b02d29 drm/i915: Fix DP-MST crtc_mask
8a0acb1f6f18 drm/i915: Add for_each_new_intel_connector_in_state()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:26: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+		for_each_if ((__state)->base.connectors[__i].ptr && \

-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \

-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

total: 1 errors, 3 warnings, 2 checks, 14 lines checked
c29f6126d5bc drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

total: 0 errors, 1 warnings, 3 checks, 15 lines checked
e5990121b4b6 drm/i915: Disable pipes in reverse order
08b6786f83a9 drm/i915/tgl: Select master transcoder in DP MST
6a6b80f2fb18 drm/i915/tgl: Introduce initial Tiger Lake workarounds
c77dbff20a84 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
6cdda9b265af drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
94baf2b17b36 drm/i915/tgl: Register state context definition for Gen12
df4c77de5dd1 drm/i915/tgl: move DP_TP_* to transcoder
d0ca1f27b4a0 drm/i915/tgl: Implement TGL DisplayPort training sequence
86de648919da HACK: drm/i915/tgl: Gen12 render context size
bfbb493106a1 drm/i915/tgl: add Gen12 default indirect ctx offset
bde4c00b75c9 drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
5453b392d597 drm/i915/tgl: Gen12 csb support
230eba25e017 drm/i915/tgl: Report valid VDBoxes with SFC capability
623edef0032b rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
240a129f0132 drm/i915/tgl: Updated Private PAT programming
ea7621575fd9 drm/i915/tgl/perf: use the same oa ctx_id format as icl
493819143bc7 drm/i915/perf: add a parameter to control the size of OA buffer
6614f3d1a6f2 drm/i915/tgl: Add perf support on TGL
-:546: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#546: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 610 lines checked
722ded5b9285 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
ed7414e63958 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
4d432593e93d drm/i915/tgl: Gen-12 render decompression
523159de2114 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
32fc1d4b22a3 drm/i915/tgl: Gen-12 media compression
-:74: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2523:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 1 warnings, 0 checks, 134 lines checked
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: disable DDIC
Okay!

Commit: drm/i915/tgl: add support for reading the timestamp frequency
Okay!

Commit: drm/i915/tgl: Move transcoders to pipes' powerwells
Okay!

Commit: drm/i915/tgl: update DMC firmware to 2.04
Okay!

Commit: drm/i915/psr: Make PSR registers relative to transcoders
Okay!

Commit: drm/i915: Add transcoder restriction to PSR2
Okay!

Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!

Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2
Okay!

Commit: drm/i915/tgl: PSR link standby is not supported anymore
Okay!

Commit: drm/i915/tgl: Access the right register when handling PSR interruptions
Okay!

Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Okay!

Commit: drm/i915: Fix DP-MST crtc_mask
Okay!

Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!

Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Okay!

Commit: drm/i915: Disable pipes in reverse order
Okay!

Commit: drm/i915/tgl: Select master transcoder in DP MST
Okay!

Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Okay!

Commit: drm/i915/tgl: Register state context definition for Gen12
Okay!

Commit: drm/i915/tgl: move DP_TP_* to transcoder
Okay!

Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence
Okay!

Commit: HACK: drm/i915/tgl: Gen12 render context size
Okay!

Commit: drm/i915/tgl: add Gen12 default indirect ctx offset
Okay!

Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Okay!

Commit: drm/i915/tgl: Gen12 csb support
Okay!

Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability
Okay!

Commit: rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Updated Private PAT programming
Okay!

Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl
Okay!

Commit: drm/i915/perf: add a parameter to control the size of OA buffer
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216

Commit: drm/i915/tgl: Add perf support on TGL
Okay!

Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
Okay!
THIS SERIES REVISION IS A RERUN. Please don't overuse the "test again" button.

Patches download mbox

# Name Submitter State A F R T
[v2,01/40] drm/i915/tgl: disable DDIC Lucas De Marchi Accepted
[v2,02/40] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi Accepted 1
[v2,03/40] drm/i915/tgl: Move transcoders to pipes' powerwells Lucas De Marchi Accepted 1
[v2,04/40] drm/i915/tgl: update DMC firmware to 2.04 Lucas De Marchi Accepted 1
[v2,05/40] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi Superseded
[v2,06/40] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi Superseded
[v2,07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi Superseded
[v2,08/40] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi New
[v2,09/40] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi New
[v2,10/40] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi New
[v2,11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi New
[v2,12/40] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi New
[v2,13/40] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi New
[v2,14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi New
[v2,15/40] drm/i915: Fix DP-MST crtc_mask Lucas De Marchi New 1
[v2,16/40] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi New 1
[v2,17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi New 1
[v2,18/40] drm/i915: Disable pipes in reverse order Lucas De Marchi New 1
[v2,19/40] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi New 1
[v2,20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi New 1
[v2,21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi New 1
[v2,22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi New
[v2,23/40] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi New
[v2,24/40] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi New
[v2,25/40] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi New 1
[v2,26/40] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi New 1
[v2,27/40] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi New 1
[v2,28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi New 1
[v2,29/40] drm/i915/tgl: Gen12 csb support Lucas De Marchi New 1
[v2,30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi New 1
[v2,31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi New 1
[v2,32/40] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi New 1
[v2,33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi New
[v2,34/40] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi New
[v2,35/40] drm/i915/tgl: Add perf support on TGL Lucas De Marchi New
[v2,36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi New
[v2,37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi New 1
[v2,38/40] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi New
[v2,39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi New 1
[v2,40/40] drm/i915/tgl: Gen-12 media compression Lucas De Marchi New 1

Tests

CI Bug Log - changes from CI_DRM_6743 -> Patchwork_14094
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14094:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_parallel@basic:
    - {fi-tgl-u}:         NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/fi-tgl-u/igt@gem_exec_parallel@basic.html

  * igt@gem_render_linear_blits@basic:
    - {fi-tgl-u}:         NOTRUN -> [SKIP][2] +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/fi-tgl-u/igt@gem_render_linear_blits@basic.html

  * igt@gem_sync@basic-all:
    - {fi-tgl-u}:         NOTRUN -> [INCOMPLETE][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/fi-tgl-u/igt@gem_sync@basic-all.html

  * igt@runner@aborted:
    - {fi-cml-h}:         NOTRUN -> [FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/fi-cml-h/igt@runner@aborted.html

  
New tests
---------

  New tests have been introduced between CI_DRM_6743 and Patchwork_14094:

### New IGT tests (2) ###

  * igt@dmabuf@dma_fence:
    - Statuses : 34 dmesg-warn(s)
    - Exec time: [0.13, 0.21] s

  * igt@dmabuf@sanitycheck:
    - Statuses : 34 pass(s)
    - Exec time: [0.01, 0.04] s

  

Known issues
------------

  Here are the changes found in Patchwork_14094 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@rcs0:
    - fi-icl-u2:          [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/fi-icl-u2/igt@gem_ctx_switch@rcs0.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [PASS][7] -> [DMESG-FAIL][8] ([fdo#111108])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108


Participating hosts (50 -> 41)
------------------------------

  Additional (1): fi-cml-h 
  Missing    (10): fi-kbl-soraka fi-kbl-7567u fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-kbl-8809g fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6743 -> Patchwork_14094

  CI-20190529: 20190529
  CI_DRM_6743: 398f53efe3d6a06633cd506d0209a69a91d0f287 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5145: 50251bcb2e8783f86ebdd86ce38adc9e3777f82f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14094: 98e274265c6dcc28a2de54649027cb0231dab79f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

98e274265c6d drm/i915/tgl: Gen-12 media compression
6866398ba290 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
3f7059412dc4 drm/i915/tgl: Gen-12 render decompression
30eb80577dd3 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
b7fb4c859fbc drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
3a5d5f60fea3 drm/i915/tgl: Add perf support on TGL
7ce3c63b50e3 drm/i915/perf: add a parameter to control the size of OA buffer
62f4069651df drm/i915/tgl/perf: use the same oa ctx_id format as icl
cab6cadef710 drm/i915/tgl: Updated Private PAT programming
68fd99478049 rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
4c6975da6450 drm/i915/tgl: Report valid VDBoxes with SFC capability
124dd207b9ab drm/i915/tgl: Gen12 csb support
2ad1cec17264 drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
b603870d172b drm/i915/tgl: add Gen12 default indirect ctx offset
157dcdad88bf HACK: drm/i915/tgl: Gen12 render context size
4801fd3cc23d drm/i915/tgl: Implement TGL DisplayPort training sequence
ad6242cf46e5 drm/i915/tgl: move DP_TP_* to transcoder
ffdeb0dcaa0a drm/i915/tgl: Register state context definition for Gen12
f16ba900d801 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
c40e6a531810 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
4a2cd76e1627 drm/i915/tgl: Introduce initial Tiger Lake workarounds
d0c351ed7a64 drm/i915/tgl: Select master transcoder in DP MST
28da8c6b55a1 drm/i915: Disable pipes in reverse order
3f922838d833 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
036e3af1fd8b drm/i915: Add for_each_new_intel_connector_in_state()
fdb7753af2b0 drm/i915: Fix DP-MST crtc_mask
756855e5f16c drm/i915/tgl: Add maximum resolution supported by PSR2 HW
e49b8d175f72 drm/i915/tgl: Access the right register when handling PSR interruptions
ac21382ff41c drm/i915/tgl: PSR link standby is not supported anymore
a5907afdadb1 drm/i915: Do not read PSR2 register in transcoders without PSR2
0d53855c280b drm/i915: Guard and warn if more than one eDP panel is present
ad641fc2c352 drm/i915/bdw+: Enable PSR in any eDP port
79c954dd51c4 drm/i915/psr: Only handle interruptions of the transcoder in use
e83d7ba515fe drm/i915: Do not unmask PSR interruption in IRQ postinstall
a482a1e8ae44 drm/i915: Add transcoder restriction to PSR2
0c2d58357955 drm/i915/psr: Make PSR registers relative to transcoders
2fd9fa5d5cec drm/i915/tgl: update DMC firmware to 2.04
90e823a21305 drm/i915/tgl: Move transcoders to pipes' powerwells
372e74bfab57 drm/i915/tgl: add support for reading the timestamp frequency
58746e12b1f7 drm/i915/tgl: disable DDIC
$ dim checkpatch origin/drm-tip
58746e12b1f7 drm/i915/tgl: disable DDIC
372e74bfab57 drm/i915/tgl: add support for reading the timestamp frequency
90e823a21305 drm/i915/tgl: Move transcoders to pipes' powerwells
2fd9fa5d5cec drm/i915/tgl: update DMC firmware to 2.04
0c2d58357955 drm/i915/psr: Make PSR registers relative to transcoders
-:428: WARNING:LONG_LINE_COMMENT: line over 100 characters
#428: FILE: drivers/gpu/drm/i915/i915_reg.h:4246:
+#define EDP_PSR_AUX_DATA(tran, i)		_MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */

total: 0 errors, 1 warnings, 0 checks, 393 lines checked
a482a1e8ae44 drm/i915: Add transcoder restriction to PSR2
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#13: 
Since BDW PSR is allowed on any port, but we need to restrict by transcoder.

total: 0 errors, 1 warnings, 0 checks, 28 lines checked
e83d7ba515fe drm/i915: Do not unmask PSR interruption in IRQ postinstall
79c954dd51c4 drm/i915/psr: Only handle interruptions of the transcoder in use
-:230: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#230: FILE: drivers/gpu/drm/i915/i915_reg.h:4227:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
+						 0 : ((trans) + 1) * 8)

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
ad641fc2c352 drm/i915/bdw+: Enable PSR in any eDP port
0d53855c280b drm/i915: Guard and warn if more than one eDP panel is present
a5907afdadb1 drm/i915: Do not read PSR2 register in transcoders without PSR2
ac21382ff41c drm/i915/tgl: PSR link standby is not supported anymore
e49b8d175f72 drm/i915/tgl: Access the right register when handling PSR interruptions
756855e5f16c drm/i915/tgl: Add maximum resolution supported by PSR2 HW
fdb7753af2b0 drm/i915: Fix DP-MST crtc_mask
036e3af1fd8b drm/i915: Add for_each_new_intel_connector_in_state()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:26: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#26: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+		for_each_if ((__state)->base.connectors[__i].ptr && \

-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \

-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

total: 1 errors, 3 warnings, 2 checks, 14 lines checked
3f922838d833 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:27: WARNING:LONG_LINE: line over 100 characters
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

total: 0 errors, 1 warnings, 3 checks, 15 lines checked
28da8c6b55a1 drm/i915: Disable pipes in reverse order
d0c351ed7a64 drm/i915/tgl: Select master transcoder in DP MST
4a2cd76e1627 drm/i915/tgl: Introduce initial Tiger Lake workarounds
c40e6a531810 drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
f16ba900d801 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
ffdeb0dcaa0a drm/i915/tgl: Register state context definition for Gen12
ad6242cf46e5 drm/i915/tgl: move DP_TP_* to transcoder
4801fd3cc23d drm/i915/tgl: Implement TGL DisplayPort training sequence
157dcdad88bf HACK: drm/i915/tgl: Gen12 render context size
b603870d172b drm/i915/tgl: add Gen12 default indirect ctx offset
2ad1cec17264 drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
124dd207b9ab drm/i915/tgl: Gen12 csb support
4c6975da6450 drm/i915/tgl: Report valid VDBoxes with SFC capability
68fd99478049 rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
cab6cadef710 drm/i915/tgl: Updated Private PAT programming
62f4069651df drm/i915/tgl/perf: use the same oa ctx_id format as icl
7ce3c63b50e3 drm/i915/perf: add a parameter to control the size of OA buffer
3a5d5f60fea3 drm/i915/tgl: Add perf support on TGL
-:546: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#546: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 610 lines checked
b7fb4c859fbc drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
30eb80577dd3 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
3f7059412dc4 drm/i915/tgl: Gen-12 render decompression
6866398ba290 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
98e274265c6d drm/i915/tgl: Gen-12 media compression
-:74: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2523:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 1 warnings, 0 checks, 134 lines checked
CI Bug Log - changes from CI_DRM_6743_full -> Patchwork_14094_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14094_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#110841])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276]) +18 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [PASS][9] -> [FAIL][10] ([fdo#105363])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-glk8/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [PASS][11] -> [INCOMPLETE][12] ([fdo#109507])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl7/igt@kms_flip@flip-vs-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#107713])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +8 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-skl:          [PASS][17] -> [INCOMPLETE][18] ([fdo#104108] / [fdo#106978])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb3/igt@kms_psr@psr2_dpms.html

  * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
    - shard-apl:          [PASS][23] -> [INCOMPLETE][24] ([fdo#103927]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-apl6/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-apl6/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@wide-bsd:
    - shard-iclb:         [SKIP][25] ([fdo#111325]) -> [PASS][26] +6 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb1/igt@gem_exec_schedule@wide-bsd.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb5/igt@gem_exec_schedule@wide-bsd.html

  * igt@gem_softpin@noreloc-interruptible:
    - shard-skl:          [TIMEOUT][27] ([fdo#111439]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl10/igt@gem_softpin@noreloc-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl1/igt@gem_softpin@noreloc-interruptible.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-glk:          [DMESG-WARN][29] ([fdo#108686]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-glk4/igt@gem_tiled_swapping@non-threaded.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-glk1/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +9 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-skl:          [INCOMPLETE][33] ([fdo#110741]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl9/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen:
    - shard-skl:          [FAIL][35] ([fdo#103232]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html

  * igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
    - shard-apl:          [INCOMPLETE][37] ([fdo#103927]) -> [PASS][38] +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-apl8/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-apl4/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][39] ([fdo#109507]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-iclb:         [INCOMPLETE][43] ([fdo#107713] / [fdo#110036 ]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb7/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb7/igt@kms_plane@pixel-format-pipe-c-planes-source-clamping.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][45] ([fdo#108145] / [fdo#110403]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_sequence@get-idle:
    - shard-hsw:          [INCOMPLETE][49] ([fdo#103540]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-hsw8/igt@kms_sequence@get-idle.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-hsw5/igt@kms_sequence@get-idle.html

  * igt@perf@blocking:
    - shard-skl:          [FAIL][51] ([fdo#110728]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl1/igt@perf@blocking.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl6/igt@perf@blocking.html

  * igt@perf@short-reads:
    - shard-kbl:          [FAIL][53] ([fdo#103183]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-kbl4/igt@perf@short-reads.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-kbl6/igt@perf@short-reads.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][55] ([fdo#109276]) -> [PASS][56] +18 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb5/igt@prime_busy@hang-bsd2.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb4/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [FAIL][57] ([fdo#111330]) -> [SKIP][58] ([fdo#109276])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
    - shard-skl:          [FAIL][59] ([fdo#108040]) -> [FAIL][60] ([fdo#103167])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6743/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14094/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103183]: https://bugs.freedesktop.org/show_bug.cgi?id=103183
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110036 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110036 
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111439]: https://bugs.freedesktop.org/show_bug.cgi?id=111439


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6743 -> Patchwork_14094

  CI-20190529: 20190529
  CI_DRM_6743: 398f53efe3d6a06633cd506d0209a69a91d0f287 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5145: 50251bcb2e8783f86ebdd86ce38adc9e3777f82f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14094: 98e274265c6dcc28a2de54649027cb0231dab79f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: disable DDIC
Okay!

Commit: drm/i915/tgl: add support for reading the timestamp frequency
Okay!

Commit: drm/i915/tgl: Move transcoders to pipes' powerwells
Okay!

Commit: drm/i915/tgl: update DMC firmware to 2.04
Okay!

Commit: drm/i915/psr: Make PSR registers relative to transcoders
Okay!

Commit: drm/i915: Add transcoder restriction to PSR2
Okay!

Commit: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!

Commit: drm/i915: Do not read PSR2 register in transcoders without PSR2
Okay!

Commit: drm/i915/tgl: PSR link standby is not supported anymore
Okay!

Commit: drm/i915/tgl: Access the right register when handling PSR interruptions
Okay!

Commit: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Okay!

Commit: drm/i915: Fix DP-MST crtc_mask
Okay!

Commit: drm/i915: Add for_each_new_intel_connector_in_state()
Okay!

Commit: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Okay!

Commit: drm/i915: Disable pipes in reverse order
Okay!

Commit: drm/i915/tgl: Select master transcoder in DP MST
Okay!

Commit: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Okay!

Commit: drm/i915/tgl: Register state context definition for Gen12
Okay!

Commit: drm/i915/tgl: move DP_TP_* to transcoder
Okay!

Commit: drm/i915/tgl: Implement TGL DisplayPort training sequence
Okay!

Commit: HACK: drm/i915/tgl: Gen12 render context size
Okay!

Commit: drm/i915/tgl: add Gen12 default indirect ctx offset
Okay!

Commit: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Okay!

Commit: drm/i915/tgl: Gen12 csb support
Okay!

Commit: drm/i915/tgl: Report valid VDBoxes with SFC capability
Okay!

Commit: rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Updated Private PAT programming
Okay!

Commit: drm/i915/tgl/perf: use the same oa ctx_id format as icl
Okay!

Commit: drm/i915/perf: add a parameter to control the size of OA buffer
-O:drivers/gpu/drm/i915/i915_perf.c:1436:15: warning: memset with byte count of 16777216
-O:drivers/gpu/drm/i915/i915_perf.c:1495:15: warning: memset with byte count of 16777216

Commit: drm/i915/tgl: Add perf support on TGL
Okay!

Commit: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
Okay!
THIS SERIES REVISION IS A RERUN. Please don't overuse the "test again" button.
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v2,01/40] drm/i915/tgl: disable DDIC Lucas De Marchi Accepted
[v2,02/40] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi Accepted 1
[v2,03/40] drm/i915/tgl: Move transcoders to pipes' powerwells Lucas De Marchi Accepted 1
[v2,04/40] drm/i915/tgl: update DMC firmware to 2.04 Lucas De Marchi Accepted 1
[v2,05/40] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi Superseded
[v2,06/40] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi Superseded
[v2,07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi Superseded
[v2,08/40] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi New
[v2,09/40] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi New
[v2,10/40] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi New
[v2,11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi New
[v2,12/40] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi New
[v2,13/40] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi New
[v2,14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi New
[v2,15/40] drm/i915: Fix DP-MST crtc_mask Lucas De Marchi New 1
[v2,16/40] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi New 1
[v2,17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi New 1
[v2,18/40] drm/i915: Disable pipes in reverse order Lucas De Marchi New 1
[v2,19/40] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi New 1
[v2,20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi New 1
[v2,21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi New 1
[v2,22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi New
[v2,23/40] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi New
[v2,24/40] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi New
[v2] drm/i915/tgl: Implement TGL DisplayPort training sequence José Roberto de Souza New
[v2,26/40] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi New 1
[v2,27/40] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi New 1
[v2,28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi New 1
[v2,29/40] drm/i915/tgl: Gen12 csb support Lucas De Marchi New 1
[v2,30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi New 1
[v2,31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi New 1
[v2,32/40] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi New 1
[v2,33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi New
[v2,34/40] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi New
[v2,35/40] drm/i915/tgl: Add perf support on TGL Lucas De Marchi New
[v2,36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi New
[v2,37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi New 1
[v2,38/40] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi New
[v2,39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi New 1
[v2,40/40] drm/i915/tgl: Gen-12 media compression Lucas De Marchi New 1

Tests

Applying: drm/i915/tgl: disable DDIC
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_display.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm/i915/tgl: add support for reading the timestamp frequency
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/intel_device_info.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_device_info.c
No changes -- Patch already applied.
Applying: drm/i915/tgl: Move transcoders to pipes' powerwells
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_display_power.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_display_power.c
No changes -- Patch already applied.
Applying: drm/i915/tgl: update DMC firmware to 2.04
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/intel_csr.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm/i915/psr: Make PSR registers relative to transcoders
Applying: drm/i915: Add transcoder restriction to PSR2
Applying: drm/i915: Do not unmask PSR interruption in IRQ postinstall
Applying: drm/i915/psr: Only handle interruptions of the transcoder in use
Applying: drm/i915/bdw+: Enable PSR in any eDP port
Applying: drm/i915: Guard and warn if more than one eDP panel is present
Applying: drm/i915: Do not read PSR2 register in transcoders without PSR2
Applying: drm/i915/tgl: PSR link standby is not supported anymore
Applying: drm/i915/tgl: Access the right register when handling PSR interruptions
Applying: drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Applying: drm/i915: Fix DP-MST crtc_mask
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_dp_mst.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm/i915: Add for_each_new_intel_connector_in_state()
Applying: drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
Applying: drm/i915: Disable pipes in reverse order
Applying: drm/i915/tgl: Select master transcoder in DP MST
Applying: drm/i915/tgl: Introduce initial Tiger Lake workarounds
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_lrc.c
M	drivers/gpu/drm/i915/gt/intel_workarounds.c
M	drivers/gpu/drm/i915/intel_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c
No changes -- Patch already applied.
Applying: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Applying: drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
Applying: drm/i915/tgl: Register state context definition for Gen12
Applying: drm/i915/tgl: move DP_TP_* to transcoder
Applying: drm/i915/tgl: Implement TGL DisplayPort training sequence
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_ddi.c
M	drivers/gpu/drm/i915/display/intel_dp.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_dp.c
Auto-merging drivers/gpu/drm/i915/display/intel_ddi.c
Applying: HACK: drm/i915/tgl: Gen12 render context size
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_engine_cs.c
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm/i915/tgl: add Gen12 default indirect ctx offset
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_lrc.c
M	drivers/gpu/drm/i915/gt/intel_lrc_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c
No changes -- Patch already applied.
Applying: drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gem/i915_gem_context.c
M	drivers/gpu/drm/i915/i915_drv.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_drv.h
No changes -- Patch already applied.
Applying: drm/i915/tgl: Gen12 csb support
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_lrc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_lrc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_lrc.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0029 drm/i915/tgl: Gen12 csb support
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
THIS SERIES REVISION IS A RERUN. Please don't overuse the "test again" button.

Patches download mbox

# Name Submitter State A F R T
[v3,01/23] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi Accepted 2
[v3,02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi Accepted 2
[v3,03/23] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi Superseded
[v3,04/23] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi Rejected 1
[v3,05/23] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi Accepted 1
[v3,06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi Accepted 1
[v3,07/23] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi New 1
[v3,08/23] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi New 1
[v3,09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi Accepted 1
[v3,10/23] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi New 1
[v3,11/23] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi Accepted 1
[v3,12/23] drm/i915: Disable pipes in reverse order Lucas De Marchi Accepted 1
[v3,13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi New 1
[v3,14/23] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi Superseded
[v3,15/23] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi Accepted 1
[v3,16/23] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi New 1
[v3,17/23] FIXME: drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi Changes Requested
[v3,18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi Accepted 1
[v3,19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi Superseded
[v3,20/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi New
[v3,21/23] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi New
[v3,22/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi New
[v3,23/23] drm/i915/tgl: Gen-12 media compression Lucas De Marchi New

Tests

CI Bug Log - changes from CI_DRM_6777 -> Patchwork_14162
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14162:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - {fi-tgl-u}:         NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-tgl-u/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_render_linear_blits@basic:
    - {fi-tgl-u}:         NOTRUN -> [SKIP][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-tgl-u/igt@gem_render_linear_blits@basic.html

  * igt@gem_sync@basic-store-all:
    - {fi-tgl-u}:         NOTRUN -> [INCOMPLETE][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-tgl-u/igt@gem_sync@basic-store-all.html

  
Known issues
------------

  Here are the changes found in Patchwork_14162 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_mmap_gtt@basic-read-no-prefault:
    - fi-icl-u3:          [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-icl-u3/igt@gem_mmap_gtt@basic-read-no-prefault.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [INCOMPLETE][6] ([fdo#103927] / [fdo#111381]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-hsw-4770r:       [DMESG-WARN][8] ([fdo#107732]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/fi-hsw-4770r/igt@i915_module_load@reload-with-fault-injection.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/fi-hsw-4770r/igt@i915_module_load@reload-with-fault-injection.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107732]: https://bugs.freedesktop.org/show_bug.cgi?id=107732
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (53 -> 44)
------------------------------

  Additional (2): fi-icl-u2 fi-gdg-551 
  Missing    (11): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-icl-y fi-bdw-samus fi-icl-dsi fi-skl-6600u fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6777 -> Patchwork_14162

  CI-20190529: 20190529
  CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14162: 62b7125d235edbae192a71d4337f9f389f6ef886 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

62b7125d235e drm/i915/tgl: Gen-12 media compression
fc2223c91ae2 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
fca4dac975ee drm/i915/tgl: Gen-12 render decompression
32f171b41ca7 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
6fd7e43b7477 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
53d10786309a drm/i915/tgl/perf: use the same oa ctx_id format as icl
5a65c5bddfa6 FIXME: drm/i915/tgl: Register state context definition for Gen12
e44fa908a435 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
82a4ff669aa6 drm/i915/tgl: Implement TGL DisplayPort training sequence
2732c013a2e5 drm/i915/tgl: move DP_TP_* to transcoder
4e72fd9a7b1a FIXME: drm/i915/tgl: Select master transcoder in DP MST
ac6110ed3d55 drm/i915: Disable pipes in reverse order
8ff0f4dfd8d7 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
04c9257c9791 drm/i915: Add for_each_new_intel_connector_in_state()
4962b6d88797 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
6c29d1d87d2d drm/i915/tgl: Access the right register when handling PSR interruptions
c7a7a115467e drm/i915/tgl: PSR link standby is not supported anymore
04f3d0338d3f drm/i915: Do not read PSR2 register in transcoders without PSR2
2c444eefb88f drm/i915: Guard and warn if more than one eDP panel is present
a2bf1ac1f4f0 drm/i915/bdw+: Enable PSR in any eDP port
01ce36bb2bfa drm/i915/psr: Only handle interruptions of the transcoder in use
2f4032c673ce drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
385d0cea263f drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
$ dim checkpatch origin/drm-tip
385d0cea263f drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
-:28: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#28: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h:87:
+#define   GEN12_GUC_TLB_INV_CR_INVALIDATE	(1<<0)
                                          	  ^

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
2f4032c673ce drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
01ce36bb2bfa drm/i915/psr: Only handle interruptions of the transcoder in use
-:230: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#230: FILE: drivers/gpu/drm/i915/i915_reg.h:4228:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
+						 0 : ((trans) + 1) * 8)

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
a2bf1ac1f4f0 drm/i915/bdw+: Enable PSR in any eDP port
2c444eefb88f drm/i915: Guard and warn if more than one eDP panel is present
04f3d0338d3f drm/i915: Do not read PSR2 register in transcoders without PSR2
c7a7a115467e drm/i915/tgl: PSR link standby is not supported anymore
6c29d1d87d2d drm/i915/tgl: Access the right register when handling PSR interruptions
4962b6d88797 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
04c9257c9791 drm/i915: Add for_each_new_intel_connector_in_state()
-:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:28: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+		for_each_if ((__state)->base.connectors[__i].ptr && \

-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \

-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

total: 1 errors, 3 warnings, 2 checks, 14 lines checked
8ff0f4dfd8d7 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

total: 0 errors, 1 warnings, 3 checks, 15 lines checked
ac6110ed3d55 drm/i915: Disable pipes in reverse order
4e72fd9a7b1a FIXME: drm/i915/tgl: Select master transcoder in DP MST
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#26: 
    Add FIXME. From Jani: double check PIPE_CONF_CHECK_I(mst_master_trans) - it's

total: 0 errors, 1 warnings, 0 checks, 325 lines checked
2732c013a2e5 drm/i915/tgl: move DP_TP_* to transcoder
82a4ff669aa6 drm/i915/tgl: Implement TGL DisplayPort training sequence
e44fa908a435 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
5a65c5bddfa6 FIXME: drm/i915/tgl: Register state context definition for Gen12
53d10786309a drm/i915/tgl/perf: use the same oa ctx_id format as icl
6fd7e43b7477 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
32f171b41ca7 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
fca4dac975ee drm/i915/tgl: Gen-12 render decompression
fc2223c91ae2 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
62b7125d235e drm/i915/tgl: Gen-12 media compression
-:74: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2523:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 1 warnings, 0 checks, 134 lines checked
CI Bug Log - changes from CI_DRM_6777_full -> Patchwork_14162_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14162_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#111325]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +6 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_pm_rpm@i2c:
    - shard-hsw:          [PASS][5] -> [FAIL][6] ([fdo#104097])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw5/igt@i915_pm_rpm@i2c.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-hsw2/igt@i915_pm_rpm@i2c.html

  * igt@i915_pm_rpm@pm-tiling:
    - shard-iclb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#108840])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@i915_pm_rpm@pm-tiling.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@i915_pm_rpm@pm-tiling.html

  * igt@i915_selftest@live_gtt:
    - shard-glk:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103359] / [k.org#198133])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-glk7/igt@i915_selftest@live_gtt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-glk2/igt@i915_selftest@live_gtt.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-iclb:         [PASS][11] -> [INCOMPLETE][12] ([fdo#107713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#105363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [PASS][15] -> [INCOMPLETE][16] ([fdo#103540])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw1/igt@kms_flip@flip-vs-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-hsw5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-iclb:         [PASS][17] -> [FAIL][18] ([fdo#103167]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_psr@psr2_dpms.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb6/igt@kms_psr@psr2_dpms.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][23] -> [FAIL][24] ([fdo#99912])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@kms_setmode@basic.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-wait-forked-busy-hang:
    - shard-apl:          [PASS][25] -> [INCOMPLETE][26] ([fdo#103927]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl5/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl7/igt@kms_vblank@pipe-c-wait-forked-busy-hang.html

  * igt@perf@polling:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#110728])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl10/igt@perf@polling.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl2/igt@perf@polling.html

  * igt@prime_busy@after-bsd2:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109276]) +16 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@prime_busy@after-bsd2.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb7/igt@prime_busy@after-bsd2.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preempt-queue-contexts-render:
    - shard-apl:          [INCOMPLETE][31] ([fdo#103927]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl8/igt@gem_exec_schedule@preempt-queue-contexts-render.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][33] ([fdo#111325]) -> [PASS][34] +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][37] ([fdo#103540]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-hsw5/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][39] ([fdo#105363]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-kbl:          [FAIL][43] ([fdo#103375]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
    - shard-skl:          [DMESG-WARN][45] ([fdo#106885]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl7/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][47] ([fdo#109642] / [fdo#111068]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][49] ([fdo#109441]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][51] ([fdo#109276]) -> [PASS][52] +4 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb2/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][53] ([fdo#111329]) -> [SKIP][54] ([fdo#109276])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb5/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [FAIL][55] ([fdo#111330]) -> [SKIP][56] ([fdo#109276])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-skl:          [FAIL][57] ([fdo#108686]) -> [SKIP][58] ([fdo#109271])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_tiled_swapping@non-threaded.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl5/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_frontbuffer_tracking@fbc-1p-rte:
    - shard-skl:          [FAIL][59] ([fdo#108040]) -> [FAIL][60] ([fdo#103167] / [fdo#110378])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14162/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-rte.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#111472]: https://bugs.freedesktop.org/show_bug.cgi?id=111472
  [fdo#111473 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111473 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (8 -> 9)
------------------------------

  Additional (1): pig-hsw-4770r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6777 -> Patchwork_14162

  CI-20190529: 20190529
  CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14162: 62b7125d235edbae192a71d4337f9f389f6ef886 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
Okay!

Commit: drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
Okay!

Commit: drm/i915/psr: Only handle interruptions of the transcoder in use
Okay!

Commit: drm/i915/bdw+: Enable PSR in any eDP port
Okay!

Commit: drm/i915: Guard and warn if more than one eDP panel is present
Okay!