intel: VK_KHR_shader_float16_int8 implementation

Submitted by Juan A. Suarez Romero on Dec. 4, 2018, 7:16 a.m.

Details

Reviewer None
Submitted Dec. 4, 2018, 7:16 a.m.
Last Updated April 17, 2019, 10:56 a.m.
Revision 16

Cover Letter(s)

Revision 1
      Hi,

this series implements support for VK_KHR_shader_float16_int8 for Intel
platforms (Broadwell and later). This extension enables Vulkan applications
to consume SPIR-V shaders that use Float16 and Int8 types in shader code,
extending the functionality included with VK_KHR_16bit_storage and
VK_KHR_8bit_storage, which was limited to load/store operations.

A branch with this series is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

On the front-end side, since the implementation targets Vulkan specifically,
it focuses mostly on the SPIR-V to NIR translator, with just a few patches
targetting NIR specifically, but most of the series targets the Intel backend
compiler.

I had sent some early code for a small part of this series a few months ago,
so some of the patches already have a Reviewed-by by Jason, but most of the
patches are either new or still unreviewed.

While the implementation targets Vulkan, the compiler backend bits are not
tied to Vulkan and should be useful for an implementation of GLSL ES mediump
using 16-bit floating point.

Following is a quick summary of the series:

- Patches 1-9 add 16-bit support to a bunch of NIR lowerings for trigonometric
and exponential builtin functions.

- Patches 10-41 implement the float16 part in the compiler backend.

- Patches 42-52 implement the int8 part in the compiler backend.

- Patches 53 to the end of the series are fixes relevant to some optimization
passes to handle properly non 32-bit cases.

This series does not include the boolean lowering to native bit-sizes yet,
since that depends on another series from Jason that hasn't landed yet. My
plan is to send that for review separately, or maybe include it to v2 of
this series at a later time.

The testing for this comes from Khronos CTS, which is okay in the sense
that it is fairly comprehensive in terms of the operations that it tests, and
even their relative precisions, but not great in the sense that this focuses
mostly on standalone tests of basic ALU operations. This means that the tests
do not usually exercise the optimizer and other parts of the compiler in the
same way that applications would, which is a coverage hole that is difficult
to address in CTS I guess. Ideally, the situation will get better once we get
an implementation of mediump, since that should hopefully enable us to test a
lot of this work with existing GLES applications. For what is worth, I am still
reviewing the compiler to identify things that need to be addressed that are not
triggered by the CTS, some of the patches in the tail of the series come from
this work and I plan to adress a few more in the coming weeks.


Review feedback is welcome!

Iago


Iago Toral Quiroga (58):
  compiler/spirv: handle 16-bit float in radians() and degrees()
  compiler/spirv: implement 16-bit asin
  compiler/spirv: implement 16-bit acos
  compiler/spirv: implement 16-bit atan
  compiler/spirv: implement 16-bit atan2
  compiler/spirv: implement 16-bit exp and log
  compiler/spirv: implement 16-bit hyperbolic trigonometric functions
  compiler/spirv: implement 16-bit frexp
  compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
  intel/compiler: implement conversions from 16-bit float to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: simplify f2*64 opcodes
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: lower 16-bit extended math to 32-bit prior to gen9
  intel/compiler: implement 16-bit fsign
  intel/compiler: allow extended math functions with HF operands
  compiler/nir: add lowering option for 16-bit fmod
  intel/compiler: lower 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  intel/compiler: lower 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: Extended Math is limited to SIMD8 on half-float
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: don't propagate HF immediates to 3-src instructions
  intel/compiler: document MAD algebraic optimization
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix 16-bit float ddx and ddy for SIMD8
  intel/compiler: do not copy-propagate strided regions to ddx/ddy
    arguments
  intel/compiler: fix ddy for half-float in gen8
  intel/compiler: workaround for SIMD8 half-float MAD in gen < 9
  compiler/spirv: add implementation to check for SpvCapabilityFloat16
    support
  anv/pipeline: support SpvCapabilityFloat16 in gen8+
  vulkan: import Khronos header and xml version 95
  anv/device: expose support for shaderFloat16 in gen8+
  anv/extensions: expose VK_KHR_shader_float16_int8 on gen8+
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: fix conversions from 64-bit to 8-bit int
  intel/compiler: implement conversions from 8-bit int to 64-bit
  intel/compiler: implement conversions from 16-bit float to 8-bit int
  intel/compiler: fix integer to/from half-float in atom platforms
  intel/compiler: assert that lower conversions produces valid strides
  intel/compiler: implement isign for int8
  intel/eu: force stride of 2 on NULL register for Byte instructions
  compiler/spirv: add implementation to check for SpvCapabilityInt8
  anv/pipeline: support SpvCapabilityInt8 in gen8+
  anv/device: expose shaderInt8 feature
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: support half-float in the combine constants pass
  intel/compiler: fix combine constants for Align16 with half-float
    prior to gen9
  intel/compiler: implement MAD algebraic optimizations on half-float
  intel/compiler: allow propagating HF immediates to MAD/LRP

Samuel Iglesias Gonsálvez (1):
  intel/compiler: Implement float64/int64 to float16 conversion

 include/vulkan/vulkan_core.h                  | 109 ++++++++-
 src/compiler/nir/nir.h                        |   2 +
 src/compiler/nir/nir_builtin_builder.h        |   8 +-
 src/compiler/nir/nir_opt_algebraic.py         |   7 +
 src/compiler/shader_info.h                    |   2 +
 src/compiler/spirv/spirv_to_nir.c             |   8 +-
 src/compiler/spirv/vtn_glsl450.c              | 183 ++++++++++----
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  25 +-
 src/intel/compiler/brw_fs.cpp                 | 161 +++++++++++--
 src/intel/compiler/brw_fs.h                   |   1 +
 .../compiler/brw_fs_cmod_propagation.cpp      |  28 +--
 .../compiler/brw_fs_combine_constants.cpp     |  82 ++++++-
 .../compiler/brw_fs_copy_propagation.cpp      |  36 ++-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  44 ++--
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 .../compiler/brw_fs_lower_conversions.cpp     |   7 +
 src/intel/compiler/brw_fs_nir.cpp             | 224 ++++++++++++++++--
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  20 +-
 src/intel/compiler/brw_reg_type.c             |  35 ++-
 src/intel/compiler/brw_reg_type.h             |  18 ++
 src/intel/compiler/brw_shader.cpp             |  20 ++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 src/vulkan/registry/vk.xml                    | 130 +++++++---
 35 files changed, 1005 insertions(+), 191 deletions(-)
    
Revision 3
      This version rebases the series on top of a more recent master and addresses
review feedback to v1.

The main change is the rewrite of the type conversion patches to reduce the
growing complexity of the backend following discussions with Jason. The main
actions I took in the end are:

1) Moved the code that handled conversion splitting into 2 conversions through
  an intermediary type to a NIR pass.
2) Added helpers to handle special conversion restrictions in the backend

Moving the splitting cases to NIR was particularly useful to reduce complexity,
since most of that complexity came from the interactions that these splitting
cases had with other restrictions.

I was also going to move the conversion code to a separate helper function, but
I think the above steps reduced the complexity to a point where this is no longer
needed. With that, said, I am happy to do this if there is still interest. For a
quick look, here is what the end result looks like:
https://github.com/Igalia/mesa/blob/itoral/VK_KHR_shader_float16_int8/src/intel/compiler/brw_fs_nir.cpp#L825

Another idea suggested for this was to just emit the conversions and then apply
the fixes during the lower_conversions pass that we run right before codegen.
I didn't try this in the end since it didn't look necessary any more, but again,
I am happy to try this if there is still interest.

The other relevant review feedback was to add new nir_{fadd,fmul}_imm helpers
and use them in the initial patches of the series. I did this for everything
except for a couple of cases where we have 'imm - expr', which we
would need to implement as neg(fadd_imm(expr, -imm)) which would add an extra
negate and didn't seem worth it.

The other relevant change is that in v1 I included support for half-float MAD/LRP
algebraic optimizations in the backend, but after some shader-db testing and 
discussion with Jason we concluded that we should actually remove these
from the backend (including 32-bit paths), so this series does this as well
(this is towards the end of the series).

A branch with this series is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (53):
  compiler/nir: add a nir_b2f() helper
  compiler/nir: add nir_fadd_imm() and nir_fadd_imm() helpers
  compiler/spirv: handle 16-bit float in radians() and degrees()
  compiler/spirv: implement 16-bit asin
  compiler/spirv: implement 16-bit acos
  compiler/spirv: implement 16-bit atan
  compiler/spirv: implement 16-bit atan2
  compiler/spirv: implement 16-bit exp and log
  compiler/spirv: implement 16-bit hyperbolic trigonometric functions
  compiler/spirv: implement 16-bit frexp
  compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: add a helper to handle conversions to 64-bit in atom
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: handle conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: lower 16-bit extended math to 32-bit prior to gen9
  intel/compiler: implement 16-bit fsign
  intel/compiler: allow extended math functions with HF operands
  compiler/nir: add lowering option for 16-bit fmod
  intel/compiler: lower 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  intel/compiler: lower 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: Extended Math is limited to SIMD8 on half-float
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: don't propagate HF immediates to 3-src instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in gen8
  intel/compiler: workaround for SIMD8 half-float MAD in gen < 9
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: handle 64-bit to 8-bit conversions
  intel/compiler: add a helper to do conversions between integer and
    half-float
  intel/compiler: handle conversions between int and half-float on atom
  intel/compiler: assert that lower conversions produces valid strides
  intel/compiler: implement isign for int8
  intel/eu: force stride of 2 on NULL register for Byte instructions
  compiler/spirv: add support for Float16 and Int8 capabilities
  anv/pipeline: support Float16 and Int8 capabilities in gen8+
  anv/device: expose shaderFloat16 and shaderInt8 in gen8+
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove MAD/LRP algebraic optimizations from the
    backend
  intel/compiler: support half-float in the combine constants pass
  intel/compiler: fix combine constants for Align16 with half-float
    prior to gen9
  intel/compiler: allow propagating HF immediates to MAD/LRP

 src/compiler/nir/nir.h                        |   2 +
 src/compiler/nir/nir_builder.h                |  24 +++
 src/compiler/nir/nir_builtin_builder.h        |   4 +-
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   2 +
 src/compiler/spirv/spirv_to_nir.c             |   8 +-
 src/compiler/spirv/vtn_glsl450.c              | 179 +++++++++++++-----
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +++-
 src/intel/compiler/brw_fs.cpp                 | 145 +++++++++-----
 src/intel/compiler/brw_fs.h                   |   1 +
 .../compiler/brw_fs_cmod_propagation.cpp      |  28 +--
 .../compiler/brw_fs_combine_constants.cpp     |  82 ++++++--
 .../compiler/brw_fs_copy_propagation.cpp      |  14 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  47 +++--
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 .../compiler/brw_fs_lower_conversions.cpp     |   7 +
 src/intel/compiler/brw_fs_nir.cpp             | 166 ++++++++++++----
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 ++-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 138 ++++++++++++++
 src/intel/compiler/brw_reg_type.c             |  35 +++-
 src/intel/compiler/brw_reg_type.h             |  18 ++
 src/intel/compiler/brw_shader.cpp             |  26 +++
 src/intel/compiler/meson.build                |   1 +
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 827 insertions(+), 218 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 4
      This version rebases the series on top of a more recent master and addresses
review feedback to v1.

The main change is the rewrite of the type conversion patches to reduce the
growing complexity of the backend following discussions with Jason. The main
actions I took in the end are:

1) Moved the code that handled conversion splitting into 2 conversions through
  an intermediary type to a NIR pass.
2) Added helpers to handle special conversion restrictions in the backend

Moving the splitting cases to NIR was particularly useful to reduce complexity,
since most of that complexity came from the interactions that these splitting
cases had with other restrictions.

I was also going to move the conversion code to a separate helper function, but
I think the above steps reduced the complexity to a point where this is no longer
needed. With that, said, I am happy to do this if there is still interest. For a
quick look, here is what the end result looks like:
https://github.com/Igalia/mesa/blob/itoral/VK_KHR_shader_float16_int8/src/intel/compiler/brw_fs_nir.cpp#L825

Another idea suggested for this was to just emit the conversions and then apply
the fixes during the lower_conversions pass that we run right before codegen.
I didn't try this in the end since it didn't look necessary any more, but again,
I am happy to try this if there is still interest.

The other relevant review feedback was to add new nir_{fadd,fmul}_imm helpers
and use them in the initial patches of the series. I did this for everything
except for a couple of cases where we have 'imm - expr', which we
would need to implement as neg(fadd_imm(expr, -imm)) which would add an extra
negate and didn't seem worth it.

The other relevant change is that in v1 I included support for half-float MAD/LRP
algebraic optimizations in the backend, but after some shader-db testing and 
discussion with Jason we concluded that we should actually remove these
from the backend (including 32-bit paths), so this series does this as well
(this is towards the end of the series).

A branch with this series is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (53):
  compiler/nir: add a nir_b2f() helper
  compiler/nir: add nir_fadd_imm() and nir_fadd_imm() helpers
  compiler/spirv: handle 16-bit float in radians() and degrees()
  compiler/spirv: implement 16-bit asin
  compiler/spirv: implement 16-bit acos
  compiler/spirv: implement 16-bit atan
  compiler/spirv: implement 16-bit atan2
  compiler/spirv: implement 16-bit exp and log
  compiler/spirv: implement 16-bit hyperbolic trigonometric functions
  compiler/spirv: implement 16-bit frexp
  compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: add a helper to handle conversions to 64-bit in atom
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: handle conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: lower 16-bit extended math to 32-bit prior to gen9
  intel/compiler: implement 16-bit fsign
  intel/compiler: allow extended math functions with HF operands
  compiler/nir: add lowering option for 16-bit fmod
  intel/compiler: lower 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  intel/compiler: lower 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: Extended Math is limited to SIMD8 on half-float
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: don't propagate HF immediates to 3-src instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in gen8
  intel/compiler: workaround for SIMD8 half-float MAD in gen < 9
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: handle 64-bit to 8-bit conversions
  intel/compiler: add a helper to do conversions between integer and
    half-float
  intel/compiler: handle conversions between int and half-float on atom
  intel/compiler: assert that lower conversions produces valid strides
  intel/compiler: implement isign for int8
  intel/eu: force stride of 2 on NULL register for Byte instructions
  compiler/spirv: add support for Float16 and Int8 capabilities
  anv/pipeline: support Float16 and Int8 capabilities in gen8+
  anv/device: expose shaderFloat16 and shaderInt8 in gen8+
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove MAD/LRP algebraic optimizations from the
    backend
  intel/compiler: support half-float in the combine constants pass
  intel/compiler: fix combine constants for Align16 with half-float
    prior to gen9
  intel/compiler: allow propagating HF immediates to MAD/LRP

 src/compiler/nir/nir.h                        |   2 +
 src/compiler/nir/nir_builder.h                |  24 +++
 src/compiler/nir/nir_builtin_builder.h        |   4 +-
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   2 +
 src/compiler/spirv/spirv_to_nir.c             |   8 +-
 src/compiler/spirv/vtn_glsl450.c              | 179 +++++++++++++-----
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +++-
 src/intel/compiler/brw_fs.cpp                 | 145 +++++++++-----
 src/intel/compiler/brw_fs.h                   |   1 +
 .../compiler/brw_fs_cmod_propagation.cpp      |  28 +--
 .../compiler/brw_fs_combine_constants.cpp     |  82 ++++++--
 .../compiler/brw_fs_copy_propagation.cpp      |  14 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  47 +++--
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 .../compiler/brw_fs_lower_conversions.cpp     |   7 +
 src/intel/compiler/brw_fs_nir.cpp             | 166 ++++++++++++----
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 ++-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 138 ++++++++++++++
 src/intel/compiler/brw_reg_type.c             |  35 +++-
 src/intel/compiler/brw_reg_type.h             |  18 ++
 src/intel/compiler/brw_shader.cpp             |  26 +++
 src/intel/compiler/meson.build                |   1 +
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 827 insertions(+), 218 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 5
      This version rebases the series on top of a more recent master and addresses
review feedback to v1.

The main change is the rewrite of the type conversion patches to reduce the
growing complexity of the backend following discussions with Jason. The main
actions I took in the end are:

1) Moved the code that handled conversion splitting into 2 conversions through
  an intermediary type to a NIR pass.
2) Added helpers to handle special conversion restrictions in the backend

Moving the splitting cases to NIR was particularly useful to reduce complexity,
since most of that complexity came from the interactions that these splitting
cases had with other restrictions.

I was also going to move the conversion code to a separate helper function, but
I think the above steps reduced the complexity to a point where this is no longer
needed. With that, said, I am happy to do this if there is still interest. For a
quick look, here is what the end result looks like:
https://github.com/Igalia/mesa/blob/itoral/VK_KHR_shader_float16_int8/src/intel/compiler/brw_fs_nir.cpp#L825

Another idea suggested for this was to just emit the conversions and then apply
the fixes during the lower_conversions pass that we run right before codegen.
I didn't try this in the end since it didn't look necessary any more, but again,
I am happy to try this if there is still interest.

The other relevant review feedback was to add new nir_{fadd,fmul}_imm helpers
and use them in the initial patches of the series. I did this for everything
except for a couple of cases where we have 'imm - expr', which we
would need to implement as neg(fadd_imm(expr, -imm)) which would add an extra
negate and didn't seem worth it.

The other relevant change is that in v1 I included support for half-float MAD/LRP
algebraic optimizations in the backend, but after some shader-db testing and 
discussion with Jason we concluded that we should actually remove these
from the backend (including 32-bit paths), so this series does this as well
(this is towards the end of the series).

A branch with this series is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (53):
  compiler/nir: add a nir_b2f() helper
  compiler/nir: add nir_fadd_imm() and nir_fadd_imm() helpers
  compiler/spirv: handle 16-bit float in radians() and degrees()
  compiler/spirv: implement 16-bit asin
  compiler/spirv: implement 16-bit acos
  compiler/spirv: implement 16-bit atan
  compiler/spirv: implement 16-bit atan2
  compiler/spirv: implement 16-bit exp and log
  compiler/spirv: implement 16-bit hyperbolic trigonometric functions
  compiler/spirv: implement 16-bit frexp
  compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: add a helper to handle conversions to 64-bit in atom
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: handle conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: lower 16-bit extended math to 32-bit prior to gen9
  intel/compiler: implement 16-bit fsign
  intel/compiler: allow extended math functions with HF operands
  compiler/nir: add lowering option for 16-bit fmod
  intel/compiler: lower 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  intel/compiler: lower 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: Extended Math is limited to SIMD8 on half-float
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: don't propagate HF immediates to 3-src instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in gen8
  intel/compiler: workaround for SIMD8 half-float MAD in gen < 9
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: handle 64-bit to 8-bit conversions
  intel/compiler: add a helper to do conversions between integer and
    half-float
  intel/compiler: handle conversions between int and half-float on atom
  intel/compiler: assert that lower conversions produces valid strides
  intel/compiler: implement isign for int8
  intel/eu: force stride of 2 on NULL register for Byte instructions
  compiler/spirv: add support for Float16 and Int8 capabilities
  anv/pipeline: support Float16 and Int8 capabilities in gen8+
  anv/device: expose shaderFloat16 and shaderInt8 in gen8+
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove MAD/LRP algebraic optimizations from the
    backend
  intel/compiler: support half-float in the combine constants pass
  intel/compiler: fix combine constants for Align16 with half-float
    prior to gen9
  intel/compiler: allow propagating HF immediates to MAD/LRP

 src/compiler/nir/nir.h                        |   2 +
 src/compiler/nir/nir_builder.h                |  24 +++
 src/compiler/nir/nir_builtin_builder.h        |   4 +-
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   2 +
 src/compiler/spirv/spirv_to_nir.c             |   8 +-
 src/compiler/spirv/vtn_glsl450.c              | 179 +++++++++++++-----
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +++-
 src/intel/compiler/brw_fs.cpp                 | 145 +++++++++-----
 src/intel/compiler/brw_fs.h                   |   1 +
 .../compiler/brw_fs_cmod_propagation.cpp      |  28 +--
 .../compiler/brw_fs_combine_constants.cpp     |  82 ++++++--
 .../compiler/brw_fs_copy_propagation.cpp      |  14 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  47 +++--
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 .../compiler/brw_fs_lower_conversions.cpp     |   7 +
 src/intel/compiler/brw_fs_nir.cpp             | 166 ++++++++++++----
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 ++-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 138 ++++++++++++++
 src/intel/compiler/brw_reg_type.c             |  35 +++-
 src/intel/compiler/brw_reg_type.h             |  18 ++
 src/intel/compiler/brw_shader.cpp             |  26 +++
 src/intel/compiler/meson.build                |   1 +
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 827 insertions(+), 218 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 6
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 7
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 8
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 9
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 10
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 11
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 12
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 13
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 14
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 15
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    
Revision 16
      The changes in this version address review feedback to v3. The most significant
changes include:

1. A more generic constant combining pass that can handle more
constant types (not just F and HF) requested by Jason.

2. The addition of assembly validation for half-float restrictions, and also
for mixed float mode, requested by Curro. It should be noted that this
implementation of VK_KHR_shader_float16_int8 does not emit any mixed mode float
instructions at this moment so I have not empirically validated the restictions
implemented here.

As always, a branch with these patches is available for testing in the
itoral/VK_KHR_shader_float16_int8 branch of the Igalia Mesa repository at
https://github.com/Igalia/mesa.

Iago Toral Quiroga (40):
  compiler/nir: add an is_conversion field to nir_op_info
  intel/compiler: add a NIR pass to lower conversions
  intel/compiler: split float to 64-bit opcodes from int to 64-bit
  intel/compiler: handle b2i/b2f with other integer conversion opcodes
  intel/compiler: assert restrictions on conversions to half-float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: handle extended math restrictions for half-float
  intel/compiler: implement 16-bit fsign
  intel/compiler: drop unnecessary temporary from 32-bit fsign
    implementation
  compiler/nir: add lowering option for 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  compiler/nir: add lowering for 16-bit ldexp
  intel/compiler: add instruction setters for Src1Type and Src2Type.
  intel/compiler: add new half-float register type for 3-src
    instructions
  intel/compiler: don't compact 3-src instructions with Src1Type or
    Src2Type bits
  intel/compiler: allow half-float on 3-source instructions since gen8
  intel/compiler: set correct precision fields for 3-source float
    instructions
  intel/compiler: fix ddx and ddy for 16-bit float
  intel/compiler: fix ddy for half-float in Broadwell
  intel/compiler: workaround for SIMD8 half-float MAD in gen8
  intel/compiler: split is_partial_write() into two variants
  intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
  intel/compiler: rework conversion opcodes
  intel/compiler: implement isign for int8
  intel/compiler: ask for an integer type if requesting an 8-bit type
  intel/eu: force stride of 2 on NULL register for Byte instructions
  intel/compiler: generalize the combine constants pass
  intel/compiler: implement is_zero, is_one, is_negative_one for
    8-bit/16-bit
  intel/compiler: add a brw_reg_type_is_integer helper
  intel/compiler: fix cmod propagation for non 32-bit types
  intel/compiler: remove inexact algebraic optimizations from the
    backend
  intel/compiler: skip MAD algebraic optimization for half-float or
    mixed mode
  intel/compiler: also set F execution type for mixed float mode in BDW
  intel/compiler: validate region restrictions for half-float
    conversions
  intel/compiler: validate conversions between 64-bit and 8-bit types
  intel/compiler: skip validating restrictions on operand types for
    mixed float
  intel/compiler: validate region restrictions for mixed float mode
  compiler/spirv: move the check for Int8 capability
  anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
  anv/device: expose VK_KHR_shader_float16_int8 in gen8+

 src/compiler/nir/nir.h                        |   5 +
 src/compiler/nir/nir_opcodes.py               |  73 +-
 src/compiler/nir/nir_opcodes_c.py             |   1 +
 src/compiler/nir/nir_opt_algebraic.py         |  11 +-
 src/compiler/shader_info.h                    |   1 +
 src/compiler/spirv/spirv_to_nir.c             |  11 +-
 src/intel/Makefile.sources                    |   1 +
 src/intel/compiler/brw_compiler.c             |   2 +
 src/intel/compiler/brw_eu_compact.c           |   5 +-
 src/intel/compiler/brw_eu_emit.c              |  36 +-
 src/intel/compiler/brw_eu_validate.c          | 396 ++++++++-
 src/intel/compiler/brw_fs.cpp                 | 101 ++-
 .../compiler/brw_fs_cmod_propagation.cpp      |  34 +-
 .../compiler/brw_fs_combine_constants.cpp     | 202 ++++-
 .../compiler/brw_fs_copy_propagation.cpp      |   8 +-
 src/intel/compiler/brw_fs_cse.cpp             |   3 +-
 .../compiler/brw_fs_dead_code_eliminate.cpp   |   2 +-
 src/intel/compiler/brw_fs_generator.cpp       |  54 +-
 src/intel/compiler/brw_fs_live_variables.cpp  |   2 +-
 src/intel/compiler/brw_fs_lower_regioning.cpp |  39 +-
 src/intel/compiler/brw_fs_nir.cpp             |  87 +-
 src/intel/compiler/brw_fs_reg_allocate.cpp    |   2 +-
 .../compiler/brw_fs_register_coalesce.cpp     |   2 +-
 .../compiler/brw_fs_saturate_propagation.cpp  |   7 +-
 src/intel/compiler/brw_fs_sel_peephole.cpp    |   4 +-
 src/intel/compiler/brw_inst.h                 |   2 +
 src/intel/compiler/brw_ir_fs.h                |   3 +-
 src/intel/compiler/brw_nir.c                  |  22 +-
 src/intel/compiler/brw_nir.h                  |   2 +
 .../compiler/brw_nir_lower_conversions.c      | 158 ++++
 src/intel/compiler/brw_reg_type.c             |   4 +
 src/intel/compiler/brw_reg_type.h             |  18 +
 src/intel/compiler/brw_shader.cpp             |  26 +
 src/intel/compiler/meson.build                |   1 +
 src/intel/compiler/test_eu_validate.cpp       | 786 ++++++++++++++++++
 src/intel/vulkan/anv_device.c                 |   9 +
 src/intel/vulkan/anv_extensions.py            |   1 +
 src/intel/vulkan/anv_pipeline.c               |   2 +
 38 files changed, 1907 insertions(+), 216 deletions(-)
 create mode 100644 src/intel/compiler/brw_nir_lower_conversions.c
    

Revisions

Patches download mbox

# Name Submitter State A F R T
[01/59] compiler/spirv: handle 16-bit float in radians() and degrees() Iago Toral Quiroga New 1
[02/59] compiler/spirv: implement 16-bit asin Iago Toral Quiroga New
[03/59] compiler/spirv: implement 16-bit acos Iago Toral Quiroga New
[04/59] compiler/spirv: implement 16-bit atan Iago Toral Quiroga New
[05/59] compiler/spirv: implement 16-bit atan2 Iago Toral Quiroga New
[06/59] compiler/spirv: implement 16-bit exp and log Iago Toral Quiroga New 1
[07/59] compiler/spirv: implement 16-bit hyperbolic trigonometric functions Iago Toral Quiroga New
[08/59] compiler/spirv: implement 16-bit frexp Iago Toral Quiroga New 1
[09/59] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin() Iago Toral Quiroga New
[10/59] intel/compiler: implement conversions from 16-bit float to 64-bit Iago Toral Quiroga New 1
[11/59] intel/compiler: Implement float64/int64 to float16 conversion Iago Toral Quiroga New
[12/59] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[13/59] intel/compiler: simplify f2*64 opcodes Iago Toral Quiroga New
[14/59] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[15/59] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 Iago Toral Quiroga New 1
[16/59] intel/compiler: implement 16-bit fsign Iago Toral Quiroga New 1
[17/59] intel/compiler: allow extended math functions with HF operands Iago Toral Quiroga New 1
[18/59] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga New 1
[19/59] intel/compiler: lower 16-bit fmod Iago Toral Quiroga New 1
[20/59] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga New 1
[21/59] intel/compiler: lower 16-bit flrp Iago Toral Quiroga New 1
[22/59] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[23/59] intel/compiler: Extended Math is limited to SIMD8 on half-float Iago Toral Quiroga New 1
[24/59] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga Accepted 1
[25/59] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga New
[26/59] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga Accepted 1
[27/59] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga Accepted 1
[28/59] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga New 1
[29/59] intel/compiler: don't propagate HF immediates to 3-src instructions Iago Toral Quiroga New 1
[30/59] intel/compiler: document MAD algebraic optimization Iago Toral Quiroga New 1
[31/59] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New
[32/59] intel/compiler: fix 16-bit float ddx and ddy for SIMD8 Iago Toral Quiroga New 1
[33/59] intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments Iago Toral Quiroga Accepted 1
[34/59] intel/compiler: fix ddy for half-float in gen8 Iago Toral Quiroga New 1
[35/59] intel/compiler: workaround for SIMD8 half-float MAD in gen < 9 Iago Toral Quiroga New
[36/59] compiler/spirv: add implementation to check for SpvCapabilityFloat16 support Iago Toral Quiroga New 1
[37/59] anv/pipeline: support SpvCapabilityFloat16 in gen8+ Iago Toral Quiroga New
[38/59] vulkan: import Khronos header and xml version 95 Iago Toral Quiroga New
[39/59] anv/device: expose support for shaderFloat16 in gen8+ Iago Toral Quiroga New 1
[40/59] anv/extensions: expose VK_KHR_shader_float16_int8 on gen8+ Iago Toral Quiroga New
[41/59] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[42/59] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga Accepted 1
[43/59] intel/compiler: fix conversions from 64-bit to 8-bit int Iago Toral Quiroga New
[44/59] intel/compiler: implement conversions from 8-bit int to 64-bit Iago Toral Quiroga New
[45/59] intel/compiler: implement conversions from 16-bit float to 8-bit int Iago Toral Quiroga New
[46/59] intel/compiler: fix integer to/from half-float in atom platforms Iago Toral Quiroga New
[47/59] intel/compiler: assert that lower conversions produces valid strides Iago Toral Quiroga New
[48/59] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[49/59] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga New 1
[50/59] compiler/spirv: add implementation to check for SpvCapabilityInt8 Iago Toral Quiroga New
[51/59] anv/pipeline: support SpvCapabilityInt8 in gen8+ Iago Toral Quiroga New
[52/59] anv/device: expose shaderInt8 feature Iago Toral Quiroga New
[53/59] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New
[54/59] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga New 1
[55/59] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New
[56/59] intel/compiler: support half-float in the combine constants pass Iago Toral Quiroga New
[57/59] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 Iago Toral Quiroga New
[58/59] intel/compiler: implement MAD algebraic optimizations on half-float Iago Toral Quiroga New
[59/59] intel/compiler: allow propagating HF immediates to MAD/LRP Iago Toral Quiroga New

Patches download mbox

# Name Submitter State A F R T
[01/59] compiler/spirv: handle 16-bit float in radians() and degrees() Iago Toral Quiroga New 1
[02/59] compiler/spirv: implement 16-bit asin Iago Toral Quiroga New
[03/59] compiler/spirv: implement 16-bit acos Iago Toral Quiroga New
[04/59] compiler/spirv: implement 16-bit atan Iago Toral Quiroga New
[05/59] compiler/spirv: implement 16-bit atan2 Iago Toral Quiroga New
[06/59] compiler/spirv: implement 16-bit exp and log Iago Toral Quiroga New 1
[07/59] compiler/spirv: implement 16-bit hyperbolic trigonometric functions Iago Toral Quiroga New
[08/59] compiler/spirv: implement 16-bit frexp Iago Toral Quiroga New 1
[09/59] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin() Iago Toral Quiroga New
[10/59] intel/compiler: implement conversions from 16-bit float to 64-bit Iago Toral Quiroga New 1
[11/59] intel/compiler: Implement float64/int64 to float16 conversion Iago Toral Quiroga New
[12/59] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[13/59] intel/compiler: simplify f2*64 opcodes Iago Toral Quiroga New
[14/59] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[15/59] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 Iago Toral Quiroga New 1
[16/59] intel/compiler: implement 16-bit fsign Iago Toral Quiroga New 1
[17/59] intel/compiler: allow extended math functions with HF operands Iago Toral Quiroga New 1
[18/59] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga New 1
[19/59] intel/compiler: lower 16-bit fmod Iago Toral Quiroga New 1
[20/59] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga New 1
[21/59] intel/compiler: lower 16-bit flrp Iago Toral Quiroga New 1
[22/59] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[23/59] intel/compiler: Extended Math is limited to SIMD8 on half-float Iago Toral Quiroga New 1
[24/59] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga Accepted 1
[25/59] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga New
[26/59] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga Accepted 1
[27/59] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga Accepted 1
[28/59] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga New 1
[29/59] intel/compiler: don't propagate HF immediates to 3-src instructions Iago Toral Quiroga New 1
[30/59] intel/compiler: document MAD algebraic optimization Iago Toral Quiroga New 1
[31/59] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New
[32/59] intel/compiler: fix 16-bit float ddx and ddy for SIMD8 Iago Toral Quiroga New 1
[33/59] intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments Iago Toral Quiroga Accepted 1
[34/59] intel/compiler: fix ddy for half-float in gen8 Iago Toral Quiroga New 1
[35/59] intel/compiler: workaround for SIMD8 half-float MAD in gen < 9 Iago Toral Quiroga New
[36/59] compiler/spirv: add implementation to check for SpvCapabilityFloat16 support Iago Toral Quiroga New 1
[37/59] anv/pipeline: support SpvCapabilityFloat16 in gen8+ Iago Toral Quiroga New
[38/59] vulkan: import Khronos header and xml version 95 Iago Toral Quiroga New
[39/59] anv/device: expose support for shaderFloat16 in gen8+ Iago Toral Quiroga New 1
[40/59] anv/extensions: expose VK_KHR_shader_float16_int8 on gen8+ Iago Toral Quiroga New
[41/59] intel/compiler: split is_partial_write() into two variants Topi Pohjolainen New 1
[42/59] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga Accepted 1
[43/59] intel/compiler: fix conversions from 64-bit to 8-bit int Iago Toral Quiroga New
[44/59] intel/compiler: implement conversions from 8-bit int to 64-bit Iago Toral Quiroga New
[45/59] intel/compiler: implement conversions from 16-bit float to 8-bit int Iago Toral Quiroga New
[46/59] intel/compiler: fix integer to/from half-float in atom platforms Iago Toral Quiroga New
[47/59] intel/compiler: assert that lower conversions produces valid strides Iago Toral Quiroga New
[48/59] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[49/59] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga New 1
[50/59] compiler/spirv: add implementation to check for SpvCapabilityInt8 Iago Toral Quiroga New
[51/59] anv/pipeline: support SpvCapabilityInt8 in gen8+ Iago Toral Quiroga New
[52/59] anv/device: expose shaderInt8 feature Iago Toral Quiroga New
[53/59] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New
[54/59] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga New 1
[55/59] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New
[56/59] intel/compiler: support half-float in the combine constants pass Iago Toral Quiroga New
[57/59] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 Iago Toral Quiroga New
[58/59] intel/compiler: implement MAD algebraic optimizations on half-float Iago Toral Quiroga New
[59/59] intel/compiler: allow propagating HF immediates to MAD/LRP Iago Toral Quiroga New

Patches download mbox

# Name Submitter State A F R T
[v2,01/53] compiler/nir: add a nir_b2f() helper Iago Toral Quiroga New
[v2,02/53] compiler/nir: add nir_fadd_imm() and nir_fadd_imm() helpers Iago Toral Quiroga New
[v2,03/53] compiler/spirv: handle 16-bit float in radians() and degrees() Iago Toral Quiroga Accepted 1
[v2,04/53] compiler/spirv: implement 16-bit asin Iago Toral Quiroga New
[v2,05/53] compiler/spirv: implement 16-bit acos Iago Toral Quiroga New
[v2,06/53] compiler/spirv: implement 16-bit atan Iago Toral Quiroga Accepted
[v2,07/53] compiler/spirv: implement 16-bit atan2 Iago Toral Quiroga Accepted
[v2,08/53] compiler/spirv: implement 16-bit exp and log Iago Toral Quiroga Accepted 1
[v2,09/53] compiler/spirv: implement 16-bit hyperbolic trigonometric functions Iago Toral Quiroga New
[v2,10/53] compiler/spirv: implement 16-bit frexp Iago Toral Quiroga New 1
[v2,11/53] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin() Iago Toral Quiroga Accepted 1
[v2,12/53] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga New 1
[v2,13/53] intel/compiler: add a helper to handle conversions to 64-bit in atom Iago Toral Quiroga New 1
[v2,14/53] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 1
[v2,15/53] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v2,16/53] intel/compiler: handle conversions to half-float Iago Toral Quiroga Accepted 1
[v2,17/53] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v2,18/53] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 Iago Toral Quiroga New 1
[v2,19/53] intel/compiler: implement 16-bit fsign Iago Toral Quiroga New 1
[v2,20/53] intel/compiler: allow extended math functions with HF operands Iago Toral Quiroga New 1
[v2,21/53] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga New 1
[v2,22/53] intel/compiler: lower 16-bit fmod Iago Toral Quiroga New 1
[v2,23/53] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga New 1
[v2,24/53] intel/compiler: lower 16-bit flrp Iago Toral Quiroga New 1
[v2,25/53] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga Accepted 2
[v2,26/53] intel/compiler: Extended Math is limited to SIMD8 on half-float Iago Toral Quiroga New 1
[v2,27/53] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1
[v2,28/53] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga New 1
[v2,29/53] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 1
[v2,30/53] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 1
[v2,31/53] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga New 1
[v2,32/53] intel/compiler: don't propagate HF immediates to 3-src instructions Iago Toral Quiroga New 1
[v2,33/53] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga Accepted 1
[v2,34/53] intel/compiler: fix ddy for half-float in gen8 Iago Toral Quiroga New 1
[v2,35/53] intel/compiler: workaround for SIMD8 half-float MAD in gen < 9 Iago Toral Quiroga New 1
[v2,36/53] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v2,37/53] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v2,38/53] intel/compiler: handle 64-bit to 8-bit conversions Iago Toral Quiroga New
[v2,39/53] intel/compiler: add a helper to do conversions between integer and half-float Iago Toral Quiroga New 1
[v2,40/53] intel/compiler: handle conversions between int and half-float on atom Iago Toral Quiroga New 1
[v2,41/53] intel/compiler: assert that lower conversions produces valid strides Iago Toral Quiroga New 1
[v2,42/53] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v2,43/53] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga New 1
[v2,44/53] compiler/spirv: add support for Float16 and Int8 capabilities Iago Toral Quiroga New 1
[v2,45/53] anv/pipeline: support Float16 and Int8 capabilities in gen8+ Iago Toral Quiroga New 1
[v2,46/53] anv/device: expose shaderFloat16 and shaderInt8 in gen8+ Iago Toral Quiroga New 1
[v2,47/53] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga Accepted
[v2,48/53] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga New 1
[v2,49/53] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New
[v2,50/53] intel/compiler: remove MAD/LRP algebraic optimizations from the backend Iago Toral Quiroga New
[v2,51/53] intel/compiler: support half-float in the combine constants pass Iago Toral Quiroga New 1
[v2,52/53] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 Iago Toral Quiroga New
[v2,53/53] intel/compiler: allow propagating HF immediates to MAD/LRP Iago Toral Quiroga New

Patches download mbox

# Name Submitter State A F R T
[v3,01/42] intel/compiler: handle conversions between int and half-float on atom Iago Toral Quiroga New 1
[v3,02/42] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga New 1
[v3,03/42] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga Accepted 2
[v3,04/42] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga Accepted 2
[v3,05/42] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v3,06/42] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v3,07/42] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 Iago Toral Quiroga New 1
[v3,08/42] intel/compiler: implement 16-bit fsign Iago Toral Quiroga New 2
[v3,09/42] intel/compiler: allow extended math functions with HF operands Iago Toral Quiroga New 1
[v3,10/42] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga New 1
[v3,11/42] intel/compiler: lower 16-bit fmod Iago Toral Quiroga New 1
[v3,12/42] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga New 1
[v3,13/42] intel/compiler: lower 16-bit flrp Iago Toral Quiroga New 1
[v3,14/42] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v3,15/42] intel/compiler: Extended Math is limited to SIMD8 on half-float Iago Toral Quiroga New 2
[v3,16/42] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 2
[v3,17/42] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga New 1
[v3,18/42] intel/compiler: add a helper function to query hardware type table Iago Toral Quiroga New
[v3,19/42] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 2
[v3,20/42] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 2
[v3,21/42] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga New 3
[v3,22/42] intel/compiler: don't propagate HF immediates to 3-src instructions Iago Toral Quiroga New 2
[v3,23/42] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v3,24/42] intel/compiler: fix ddy for half-float in gen8 Iago Toral Quiroga New 2
[v3,25/42] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v3,26/42] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v3,27/42] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v3,28/42] intel/compiler: handle 64-bit float to 8-bit integer conversions Iago Toral Quiroga New
[v3,29/42] intel/compiler: handle conversions between int and half-float on atom Iago Toral Quiroga New 1
[v3,30/42] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v3,31/42] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga New 1
[v3,32/42] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga New 1
[v3,33/42] compiler/spirv: add support for Float16 and Int8 capabilities Iago Toral Quiroga New 1
[v3,34/42] anv/pipeline: support Float16 and Int8 capabilities in gen8+ Iago Toral Quiroga New 1
[v3,35/42] anv/device: expose shaderFloat16 and shaderInt8 in gen8+ Iago Toral Quiroga New 1
[v3,36/42] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v3,37/42] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga New 1
[v3,38/42] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v3,39/42] intel/compiler: remove MAD/LRP algebraic optimizations from the backend Iago Toral Quiroga New 1
[v3,40/42] intel/compiler: support half-float in the combine constants pass Iago Toral Quiroga New 1
[v3,41/42] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 Iago Toral Quiroga New
[v3,42/42] intel/compiler: allow propagating HF immediates to MAD/LRP Iago Toral Quiroga New
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
intel/fs: Promote execution type to 32-bit when any half-float conversion is needed. Francisco Jerez Accepted 2 1
[v3,02/42] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga New 1
[v3,03/42] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga Accepted 2
[v3,04/42] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga Accepted 2
[v3,05/42] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v3,06/42] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v3,07/42] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 Iago Toral Quiroga New 1
[v3,08/42] intel/compiler: implement 16-bit fsign Iago Toral Quiroga New 2
[v3,09/42] intel/compiler: allow extended math functions with HF operands Iago Toral Quiroga New 1
[v3,10/42] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga New 1
[v3,11/42] intel/compiler: lower 16-bit fmod Iago Toral Quiroga New 1
[v3,12/42] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga New 1
[v3,13/42] intel/compiler: lower 16-bit flrp Iago Toral Quiroga New 1
[v3,14/42] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v3,15/42] intel/compiler: Extended Math is limited to SIMD8 on half-float Iago Toral Quiroga New 2
[v3,16/42] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 2
[v3,17/42] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga New 1
[v3,18/42] intel/compiler: add a helper function to query hardware type table Iago Toral Quiroga New
[v3,19/42] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 2
[v3,20/42] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 2
[v3,21/42] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga New 3
[v3,22/42] intel/compiler: don't propagate HF immediates to 3-src instructions Iago Toral Quiroga New 2
[v3,23/42] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v3,24/42] intel/compiler: fix ddy for half-float in gen8 Iago Toral Quiroga New 2
[v3,25/42] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v3,26/42] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v3,27/42] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v3,28/42] intel/compiler: handle 64-bit float to 8-bit integer conversions Iago Toral Quiroga New
[v3,29/42] intel/compiler: handle conversions between int and half-float on atom Iago Toral Quiroga New 1
[v3,30/42] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v3,31/42] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga New 1
[v3,32/42] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga New 1
[v3,33/42] compiler/spirv: add support for Float16 and Int8 capabilities Iago Toral Quiroga New 1
[v3,34/42] anv/pipeline: support Float16 and Int8 capabilities in gen8+ Iago Toral Quiroga New 1
[v3,35/42] anv/device: expose shaderFloat16 and shaderInt8 in gen8+ Iago Toral Quiroga New 1
[v3,36/42] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v3,37/42] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga New 1
[v3,38/42] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v3,39/42] intel/compiler: remove MAD/LRP algebraic optimizations from the backend Iago Toral Quiroga New 1
[v3,40/42] intel/compiler: support half-float in the combine constants pass Iago Toral Quiroga New 1
[v3,41/42] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 Iago Toral Quiroga New
[v3,42/42] intel/compiler: allow propagating HF immediates to MAD/LRP Iago Toral Quiroga New

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v4,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga New 1
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v4,33/40] intel/compiler: also set F execution type for mixed float mode in BDW Iago Toral Quiroga New
[v4,34/40] intel/compiler: validate region restrictions for half-float conversions Iago Toral Quiroga New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v4,37/40] intel/compiler: validate region restrictions for mixed float mode Iago Toral Quiroga New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v4,33/40] intel/compiler: also set F execution type for mixed float mode in BDW Iago Toral Quiroga New
[v4,34/40] intel/compiler: validate region restrictions for half-float conversions Iago Toral Quiroga New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v4,37/40] intel/compiler: validate region restrictions for mixed float mode Iago Toral Quiroga New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v5,33/40] intel/compiler: also set F execution type for mixed float mode in BDW Iago Toral Quiroga New 1
[v4,34/40] intel/compiler: validate region restrictions for half-float conversions Iago Toral Quiroga New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v4,37/40] intel/compiler: validate region restrictions for mixed float mode Iago Toral Quiroga New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v6,31/38] intel/compiler: implement SIMD16 restrictions for mixed-float instructions Juan A. Suarez Romero New
[v4,34/40] intel/compiler: validate region restrictions for half-float conversions Iago Toral Quiroga New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v4,37/40] intel/compiler: validate region restrictions for mixed float mode Iago Toral Quiroga New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v6,32/38] intel/compiler: also set F execution type for mixed float mode in BDW Juan A. Suarez Romero Accepted 1
[v4,34/40] intel/compiler: validate region restrictions for half-float conversions Iago Toral Quiroga New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v4,37/40] intel/compiler: validate region restrictions for mixed float mode Iago Toral Quiroga New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v6,32/38] intel/compiler: also set F execution type for mixed float mode in BDW Juan A. Suarez Romero Accepted 1
[v5,33/38] intel/compiler: validate region restrictions for half-float conversions Juan A. Suarez Romero New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v4,37/40] intel/compiler: validate region restrictions for mixed float mode Iago Toral Quiroga New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v6,32/38] intel/compiler: also set F execution type for mixed float mode in BDW Juan A. Suarez Romero Accepted 1
[v5,33/38] intel/compiler: validate region restrictions for half-float conversions Juan A. Suarez Romero New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v5,35/38] intel/compiler: validate region restrictions for mixed float mode Juan A. Suarez Romero New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v7,28/35] intel/compiler: implement SIMD16 restrictions for mixed-float instructions Juan A. Suarez Romero New
[v5,33/38] intel/compiler: validate region restrictions for half-float conversions Juan A. Suarez Romero New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v5,35/38] intel/compiler: validate region restrictions for mixed float mode Juan A. Suarez Romero New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v7,28/35] intel/compiler: implement SIMD16 restrictions for mixed-float instructions Juan A. Suarez Romero New
[v6,30/35] intel/compiler: validate region restrictions for half-float conversions Juan A. Suarez Romero New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v5,35/38] intel/compiler: validate region restrictions for mixed float mode Juan A. Suarez Romero New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v7,28/35] intel/compiler: implement SIMD16 restrictions for mixed-float instructions Juan A. Suarez Romero New
[v6,30/35] intel/compiler: validate region restrictions for half-float conversions Juan A. Suarez Romero New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v6,32/35] intel/compiler: validate region restrictions for mixed float mode Juan A. Suarez Romero New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[v4,01/40] compiler/nir: add an is_conversion field to nir_op_info Iago Toral Quiroga New 1
[v5,02/40] intel/compiler: add a NIR pass to lower conversions Iago Toral Quiroga Accepted 2
[v4,03/40] intel/compiler: split float to 64-bit opcodes from int to 64-bit Iago Toral Quiroga New 2
[v4,04/40] intel/compiler: handle b2i/b2f with other integer conversion opcodes Iago Toral Quiroga New 2
[v4,05/40] intel/compiler: assert restrictions on conversions to half-float Iago Toral Quiroga New 2
[v4,06/40] intel/compiler: lower some 16-bit float operations to 32-bit Iago Toral Quiroga New 2
[v4,07/40] intel/compiler: handle extended math restrictions for half-float Iago Toral Quiroga Accepted 2
[v4,08/40] intel/compiler: implement 16-bit fsign Iago Toral Quiroga Accepted 2
[v4,09/40] intel/compiler: drop unnecessary temporary from 32-bit fsign implementation Iago Toral Quiroga Accepted 1
[v4,10/40] compiler/nir: add lowering option for 16-bit fmod Iago Toral Quiroga Accepted 1
[v4,11/40] compiler/nir: add lowering for 16-bit flrp Iago Toral Quiroga Accepted 1
[v4,12/40] compiler/nir: add lowering for 16-bit ldexp Iago Toral Quiroga New 2
[v4,13/40] intel/compiler: add instruction setters for Src1Type and Src2Type. Iago Toral Quiroga New 1 2
[v4,14/40] intel/compiler: add new half-float register type for 3-src instructions Iago Toral Quiroga Accepted 2
[v4,15/40] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits Iago Toral Quiroga New 3
[v4,16/40] intel/compiler: allow half-float on 3-source instructions since gen8 Iago Toral Quiroga New 3
[v4,17/40] intel/compiler: set correct precision fields for 3-source float instructions Iago Toral Quiroga Accepted 3
[v4,18/40] intel/compiler: fix ddx and ddy for 16-bit float Iago Toral Quiroga New 2
[v4,19/40] intel/compiler: fix ddy for half-float in Broadwell Iago Toral Quiroga Accepted 2
[v4,20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8 Iago Toral Quiroga New 1
[v4,21/40] intel/compiler: split is_partial_write() into two variants Iago Toral Quiroga New
[v4,22/40] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit Iago Toral Quiroga New 1
[v4,23/40] intel/compiler: rework conversion opcodes Iago Toral Quiroga Accepted 1
[v4,24/40] intel/compiler: implement isign for int8 Iago Toral Quiroga New 1
[v4,25/40] intel/compiler: ask for an integer type if requesting an 8-bit type Iago Toral Quiroga Accepted 1
[v4,26/40] intel/eu: force stride of 2 on NULL register for Byte instructions Iago Toral Quiroga Accepted 1
[v4,27/40] intel/compiler: generalize the combine constants pass Iago Toral Quiroga New 1
[v4,28/40] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit Iago Toral Quiroga New 1
[v4,29/40] intel/compiler: add a brw_reg_type_is_integer helper Iago Toral Quiroga Accepted 1
[v4,30/40] intel/compiler: fix cmod propagation for non 32-bit types Iago Toral Quiroga New 1
[v4,31/40] intel/compiler: remove inexact algebraic optimizations from the backend Iago Toral Quiroga Accepted 1
[v4,32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode Iago Toral Quiroga Accepted 1
[v7,28/35] intel/compiler: implement SIMD16 restrictions for mixed-float instructions Juan A. Suarez Romero New
[v6,30/35] intel/compiler: validate region restrictions for half-float conversions Juan A. Suarez Romero New
[v4,35/40] intel/compiler: validate conversions between 64-bit and 8-bit types Iago Toral Quiroga New 1
[v4,36/40] intel/compiler: skip validating restrictions on operand types for mixed float Iago Toral Quiroga New
[v7] intel/compiler: validate region restrictions for mixed float mode Juan A. Suarez Romero New
[v4,38/40] compiler/spirv: move the check for Int8 capability Iago Toral Quiroga New 1
[v4,39/40] anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+ Iago Toral Quiroga New 1
[v4,40/40] anv/device: expose VK_KHR_shader_float16_int8 in gen8+ Iago Toral Quiroga New 1