Skylake DMC/DC-state fixes and redesign

Submitted by Patrik Jakobsson on Nov. 3, 2015, 12:31 p.m.

Details

Reviewer None
Submitted Nov. 3, 2015, 12:31 p.m.
Last Updated Nov. 16, 2015, 3:20 p.m.
Revision 8

Cover Letter(s)

Revision 1
      These patches should sit on top of the DMC redesign patches from
Animesh/Imre [1] which in turn depends on Mika's FW debug patches [2].

First two patches are from Ville and is included since they otherwise
might be forgotten. The third from Ville helps with handling DC off when
doing Aux A communication.

[1]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/079041.html

[2]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/078898.html

Patrik Jakobsson (5):
  drm/i915: Add a modeset power domain
  drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
  drm/i915/skl: Turn DC handling into a power well
  drm/i915/skl: Add boot parameter for disabling DC6
  drm/i915: Force loading of csr program at boot

Ville Syrjälä (3):
  drm/i915: Clean up AUX power domain handling
  drm/i915: Introduce a gmbus power domain
  drm/i915: Remove DDI power domain exclusion
    SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS

 drivers/gpu/drm/i915/i915_debugfs.c     |   4 +
 drivers/gpu/drm/i915/i915_drv.c         |   8 +-
 drivers/gpu/drm/i915/i915_drv.h         |   5 +-
 drivers/gpu/drm/i915/i915_params.c      |   6 ++
 drivers/gpu/drm/i915/intel_csr.c        |   6 +-
 drivers/gpu/drm/i915/intel_display.c    |  46 ++++++++++
 drivers/gpu/drm/i915/intel_dp.c         |  48 +++--------
 drivers/gpu/drm/i915/intel_drv.h        |   6 +-
 drivers/gpu/drm/i915/intel_hdmi.c       |   8 +-
 drivers/gpu/drm/i915/intel_i2c.c        |   6 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 148 ++++++++++++++++----------------
 11 files changed, 163 insertions(+), 128 deletions(-)
    
Revision 3
      This v2 of the series is rebased on top of a new series from Imre [1]
and contains a few new patches and reordering.

These patches should sit on top of the DMC redesign patches from
Animesh/Imre [2] which in turn depends on Mika's FW debug patches [3].

First couple of patches are from Ville and is included since they
otherwise might be forgotten. The third from Ville helps with handling
DC off when doing Aux A communication.

[1]
http://lists.freedesktop.org/archives/intel-gfx/2015-November/079412.html

[2]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/079041.html

[3]
http://lists.freedesktop.org/archives/intel-gfx/2015-October/078898.html

Patrik Jakobsson (9):
  drm/i915: Don't trust CSR program memory contents
  drm/i915/gen9: Always set mask memory up when enabling DC5 or DC6
  drm/i915: Remove distinction between DDI 2 vs 4 lanes
  drm/i915: Add a modeset power domain
  drm/i915: Do not warn on PG2 enabled in gen9_disable_dc5()
  drm/i915: Explain usage of power well IDs vs bit groups
  drm/i915/gen9: Turn DC handling into a power well
  drm/i915/gen9: Add boot parameter for disabling DC6
  drm/i915/skl: Remove unused suspend and resume callbacks

Ville Syrjälä (3):
  drm/i915: Clean up AUX power domain handling
  drm/i915: Introduce a gmbus power domain
  drm/i915: Remove DDI power domain exclusion
    SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS

 drivers/gpu/drm/i915/i915_debugfs.c     |  32 ++--
 drivers/gpu/drm/i915/i915_drv.c         |  23 ---
 drivers/gpu/drm/i915/i915_drv.h         |  17 +--
 drivers/gpu/drm/i915/i915_params.c      |   6 +
 drivers/gpu/drm/i915/i915_reg.h         |   3 +
 drivers/gpu/drm/i915/intel_csr.c        |  10 +-
 drivers/gpu/drm/i915/intel_display.c    |  56 ++++++-
 drivers/gpu/drm/i915/intel_dp.c         |  48 ++----
 drivers/gpu/drm/i915/intel_drv.h        |   4 +-
 drivers/gpu/drm/i915/intel_hdmi.c       |   8 +-
 drivers/gpu/drm/i915/intel_i2c.c        |   6 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 255 ++++++++++++++++----------------
 12 files changed, 233 insertions(+), 235 deletions(-)
    

Revisions