i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

Submitted by Iago Toral Quiroga on July 19, 2016, 10:39 a.m.

Details

Reviewer None
Submitted July 19, 2016, 10:39 a.m.
Last Updated Oct. 20, 2016, 7:10 a.m.
Revision 5

Cover Letter(s)

Revision 1
      Hi,

this series implements initial support for Haswell align16 FP64, and with that we can enable FP64 and OpenGL 4.0 in Haswell. Gen8+ is now fully scalar, so the patches focus on gen7 and Haswell specifically (although they do mention what things are not expected to work outside gen7 for future reference). IvyBridge is not covered in this series (that needs more work).

These patches are available in our repository for testing. You can clone it using the following command:

$ git clone -b i965-fp64-gen7-scalar-vec4-rc1 https://github.com/Igalia/mesa.git

The only feature missing in this series would be register spilling of 64-bit data. We are working on it but we think that can be added later. With this series all existing FP64 tests in Piglit pass on Haswell, except for ~40 tests that fail to spill registers (mostly the same varying-packing tests that failed in the scalar backend before Curro fixed the scalar spilling implementation for SIMD32).

The main issue with align16 / fp64 is that the hardware only supports 32-bit swizzles. This means that dvec components Z/W are not directly accesible using regions with a width of 4 (also, it seems that the hardware will fix DF regions to use a width of 2 anyway). In the past we have tried to split DF instructions with 3/4 components into dvec2 instructions (XY on one instruction, ZW on another) to overcome this restriction, but that won't work in cases of non-uniform control-flow, so that option was eventually discarded.

The current solution proposed by Curro keeps an exec size of 8 for DF instructions (that is, normal dvec4 SIMD4x2 execution) and does not do any kind of splitting by default. In this scenario, using source regions with a width of 2 we have 2-element rows and we can address either of the 2 elements in the row using 32-bit swizzles (XY selects the first DF component in the row, ZW the second). The problem is that not all swizzle combinations are supported. For example, we can't implement a logical swizzle like XXXX because a region such as g0<2,2,1>.XYXY would instead select the logical swizzle XXZZ. This is because with 2-wide rows the swizzle we apply is the same for both the first half of a dvec4 and the second half. There are many other problematic swizzles combinations. Dealing with this requires different combinations of instruction splitting and / or temporaries depending on the incoming swizzles.

With that strategy, accessing components Z/W in a dvec4 is still not trivial, it would require some work and probably also instruction splitting to avoid violating register region restrictions. Instead, we take advantage of a gen7 hardware decompression bug that allows us to implement Z/W swizzles without requiring instruction splitting. This behavior is documented in the corresponding patches and is activated via a specific flag (force_vstride0) that is only set in a particular lowerig pass, so that we keep this hack limited to a particular place in the driver code, should we decide to change that in the future (for example if we want to support gen8/align16). See the commit log on patch "i965/vec4: implement access to DF source components Z/W" for a detailed explanation.

To make things worse, although writemasks mostly work as 64-bit it seems that XY and ZW writemasks in particular are  32-bit, which means that there is no native representation of XY/ZW 64-bit writemasks at all and if we find these we have to split the instructions to work around them.

Because of all this, we decided that an initial implementation could just scalarize all DF instructions to work around most of these issues, with the plan of having a functioning fp64/align16 implementation as soon as possible which would still have some room for improvement in the future. This is what this series implements (with the exception of XYZW swizzles that just work). There are some "easy" swizzles we can let through without scalarization too and the plan is to add them later, and then there are some more complex scenarios that require some level of non-full scalarizarion that we can add later on too with some extra work. Curro wrote an excellent summary of the different situations we can find here [1].

Then there are also a number of relevant hardware bugs and restrictions that require additional instruction splitting. Because of that we had to implement a SIMD splitting pass similar to the one we have for the FS backend but much simpler, since we only really need to split some cases of DF instructions from an execsize of 8 to an execsize of 4.

Special thanks to Curro for all his help and insight!

[1] https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82

Connor Abbott (7):
  i965/vec4/nir: simplify glsl_type_for_nir_alu_type()
  i965/vec4/nir: allocate two registers for dvec3/dvec4
  i965/vec4/nir: fix nir_intrinsic_load_uniform for doubles
  i965/vec4/nir: set the right type for 64-bit registers
  i965/vec4: add support for printing DF immediates
  i965: add brw_vecn_grf()
  i965/vec4: don't constant propagate 64-bit immediates

Iago Toral Quiroga (81):
  i965/vec4/nir: Add bit-size information to types
  i965/vec4/nir: support doubles in ALU operations
  i965/vec4/nir: fix emitting 64-bit immediates
  i965/vec4: add double/float conversion pseudo-opcodes
  i965/vec4: translate d2f/f2d
  i965/vec4: set correct register regions for 32-bit and 64-bit
  i965/disasm: align16 DF source regions have a width of 2
  i965/vec4: We only support 32-bit integer ALU operations for now
  i965/vec4: add dst_null_df()
  i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
  i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
  i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT
  i965/vec4: don't copy propagate vector opcodes that operate in align1
    mode
  i965/vec4: implement double unpacking
  i965/vec4: implement double packing
  i965/vec4/nir: implement double comparisons
  i965/vec4: fix base offset for nir_registers with doubles
  i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations
  i965/vec4: make opt_vector_float ignore doubles
  i965/vec4: fix register allocation for 64-bit undef sources
  i965/vec4: Rename DF to/from F generator opcodes
  i965/vec4: add helpers for conversions to/from doubles
  i965/vec4: implement hardware workaround for align16 double to float
    conversion
  i965/vec4: implement d2i, d2u, i2d and u2d
  i965/vec4: implement d2b
  i965/vec4: implement fsign() for doubles
  i965/vec4: fix optimize predicate for doubles
  i965/vec4: add a helper function to create double immediates
  i965/vec4: allow the vec4 IR to indicate the execution size of
    instructions
  i965/vec4: dump the instruction execution size
  i965/vec4: add a SIMD lowering pass
  i965/vec4: make the generator set correct NibCtrl for SIMD4 DF
    instructions
  i965/vec4: dump NibCtrl for instructions with execsize 4
  i965/disasm: print NibCtrl for instructions with execsize 4
  i965/vec4: teach CSE about exec_size, group and doubles
  i965/vec4: split double-precision bcsel
  i965/vec4: add a scalarization pass for double-precision instructions
  i965/vec4: translate 64-bit swizzles to 32-bit
  i965/vec4: add a force_vstride0 flag to src_reg
  i965/vec4: implement access to DF source components Z/W
  i965/vec4: Use force_vstride0 to fix DF Z/W writes from X/Y channels
  i965/vec4: add a sanity check for force_vstride0
  i965/vec4: print subnr in dump_instruction()
  i965/disasm: fix subreg for dst in Align16 mode
  i965/vec4: fix regs_read() for doubles
  i965/vec4: teach register coalescing about 64-bit
  i965/vec4: fix regs_written for doubles
  i965/vec4: fix pack_uniform_registers for doubles
  i965/vec4: fix indentation in pack_uniform_registers
  i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands
  i965/vec4/nir: do not emit 64-bit MAD
  i965/vec4: do not emit 64-bit MAD
  i965/vec4: Add a shuffle_64bit_data helper
  i965/vec4: Fix UBO loads for 64-bit data
  i965/vec4: Fix SSBO loads for 64-bit data
  i965/vec4: Fix SSBO stores for 64-bit data
  i965/vec4: prevent copy-propagation from values with a different type
    size
  i965/vec4: Prevent copy propagation from violating pre-gen8
    restrictions
  i965/vec4: don't propagate single-precision uniforms into 4-wide
    instructions
  i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8
    platforms
  i965/vec4: Do not use DepCtrl with 64-bit instructions
  i965/vec4: do not split scratch read/write opcodes
  i965/vec4: fix scratch offset for 64bit data
  i965/vec4: fix scratch reads for 64bit data
  i965/vec4: fix scratch writes for 64bit data
  i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit
    data
  i965/vec4: fix indentation in move_push_constants_to_pull_constants()
  i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data
  i965/vec4: make emit_pull_constant_load support 64-bit loads
  i965/vec4: fix store output for 64-bit types
  i965/vec4/tcs: fix input loading for 64-bit data
  i965/vec4/tcs: fix outputs for 64-bit data
  i965/vec4/tes: fix input loading for 64bit data types
  i965/vec4/tes: fix setup_payload() for 64bit data types
  i965/vec4: split instructions that read 64-bit attrs in TessEval
  i965/vec4: fix writes to Z/W:DF from a FIXED_GRF
  i965/vec4: dump subnr for FIXED_GRF
  i965/vec4/scalarize_df: do not scalarize instructions with identity
    swizzles
  i965/vec4/scalarize_df: Always scalarize XY / ZW writemasks
  i965/vec4: enable ARB_gpu_shader_fp64 for Haswell
  i965/gen7: expose OpenGL 4.0 on Haswell

Juan A. Suarez Romero (1):
  i965/vec4: handle 32 and 64 bit channels in liveness analysis

Samuel Iglesias Gonsálvez (6):
  i965/nir: double/dvec2 uniforms only need to be padded to a single
    vec4 slot
  i965/vec4: use the new helper function to create double immediates
  i965/vec4: don't copy propagate if subnr is set
  i965/vec4: set force_vstride0 on any 64-bit source that has subnr > 0
  i965/vec4/gs: fix input loading for 64bit data
  i965/vec4: implement force_vstride0 for FIXED_GRF

 src/mesa/drivers/dri/i965/brw_defines.h            |   6 +
 src/mesa/drivers/dri/i965/brw_disasm.c             |  15 +-
 src/mesa/drivers/dri/i965/brw_ir_vec4.h            |   4 +
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp     |   3 +-
 src/mesa/drivers/dri/i965/brw_reg.h                |   6 +
 src/mesa/drivers/dri/i965/brw_shader.cpp           |  12 +
 src/mesa/drivers/dri/i965/brw_vec4.cpp             | 645 ++++++++++++++++++---
 src/mesa/drivers/dri/i965/brw_vec4.h               |  22 +
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |  59 ++
 src/mesa/drivers/dri/i965/brw_vec4_cse.cpp         |  30 +-
 .../dri/i965/brw_vec4_dead_code_eliminate.cpp      |  39 +-
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   | 110 +++-
 src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp      |  43 +-
 .../drivers/dri/i965/brw_vec4_live_variables.cpp   |  36 +-
 .../drivers/dri/i965/brw_vec4_live_variables.h     |   7 +-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp         | 629 ++++++++++++++++----
 src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp         |  56 +-
 src/mesa/drivers/dri/i965/brw_vec4_tes.cpp         |  83 ++-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp     | 167 ++++--
 src/mesa/drivers/dri/i965/intel_extensions.c       |   5 +
 src/mesa/drivers/dri/i965/intel_screen.c           |   8 +
 21 files changed, 1707 insertions(+), 278 deletions(-)
    
Revision 3
      It's been some time since we sent the first version of the patches, so here is
a v2, which adds:

1. Feedback from Curro to v1. I think the only thing missing is the suggestion
to change the semantics of the offset() helper in vec4 to match those in the
scalar backend. I sent this as a separate series [1] that is still awaiting
review. Once that is good to land we should adapt this series accordingly.

2. Adaptations to the sub-register offsets work done by Curro in master.

3. Some rudimentary support for 64-bit spilling. This is quite limited at the
moment, since it skips spilling of fp64 data in a number of cases where it
is not safe to do it at present. I guess we can look for ways improve this
going forward, but I rather do that after we land the bulk of fp64, since the
series is already quite big as it is.

4. Avoid scalarizing a number of swizzle combinations that we can support
natively.

5. Many other small clean-ups and fixes.

The series is available for testing in the 'i965-fp64-gen7-scalar-vec4-rc2'
branch of our github repository [2].

This series implements the bulk of the fp64 align16 backend support and creates
the infrastructure to implement vertex attrib 64bit as well, so once this lands
in master we plan to send additional series that add VA64 for Haswell, and then
Fp64 and VA64 for IvyBridge.

[1] https://lists.freedesktop.org/archives/mesa-dev/2016-October/130459.html
[2] https://github.com/Igalia/mesa/tree/i965-fp64-gen7-scalar-vec4-rc2

Connor Abbott (6):
  i965/vec4/nir: simplify glsl_type_for_nir_alu_type()
  i965/vec4/nir: allocate two registers for dvec3/dvec4
  i965/vec4/nir: set the right type for 64-bit registers
  i965/vec4: add support for printing DF immediates
  i965: add brw_vecn_grf()
  i965/vec4: don't constant propagate 64-bit immediates

Iago Toral Quiroga (92):
  i965/vec4/nir: Add bit-size information to types
  i965/vec4/nir: support doubles in ALU operations
  i965/vec4/nir: fix emitting 64-bit immediates
  i965/vec4: add double/float conversion pseudo-opcodes
  i965/vec4: translate d2f/f2d
  i965: fix subnr overflow in suboffset()
  i965/vec4: set correct register regions for 32-bit and 64-bit
  i965/disasm: align16 DF source regions have a width of 2
  i965/vec4: We only support 32-bit integer ALU operations for now
  i965/vec4: add dst_null_df()
  i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
  i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
  i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT
  i965/vec4: don't copy propagate vector opcodes that operate in align1
    mode
  i965/vec4: implement double unpacking
  i965/vec4: implement double packing
  i965/vec4/nir: implement double comparisons
  i965/vec4: fix base offset for nir_registers with doubles
  i965/vec4: fix indentation in get_nir_src()
  i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations
  i965/vec4: make opt_vector_float ignore doubles
  i965/vec4: fix register allocation for 64-bit undef sources
  i965/vec4: Rename DF to/from F generator opcodes
  i965/vec4: add helpers for conversions to/from doubles
  i965/vec4: implement hardware workaround for align16 double to float
    conversion
  i965/vec4: implement d2i, d2u, i2d and u2d
  i965/vec4: implement d2b
  i965/vec4: implement fsign() for doubles
  i965/vec4: fix optimize predicate for doubles
  i965/vec4: add a helper function to create double immediates
  i965: move exec_size from fs_instruction to backend_instruction
  i965/vec4: fix size_written for doubles
  i965/vec4: fix regs_read() for doubles
  i965/vec4: use the IR's execution size
  i965/vec4: dump the instruction execution size
  i965/vec4: add a horiz_offset() helper
  i965: move the group field from fs_inst to backend_instruction.
  i965/vec4: add a SIMD lowering pass
  i965/vec4: make the generator set correct NibCtrl for SIMD4 DF
    instructions
  i965/vec4: dump NibCtrl for instructions with execsize != 8
  i965/disasm: print NibCtrl for instructions with execsize < 8
  i965/vec4: teach CSE about exec_size, group and doubles
  i965/vec4: teach cmod propagation about different execution sizes
  i965/vec4: split double-precision bcsel
  i965/vec4: add a scalarization pass for double-precision instructions
  i965/vec4: translate 64-bit swizzles to 32-bit
  i965/vec4: implement access to DF source components Z/W
  i965/disasm: fix subreg for dst in Align16 mode
  i965/vec4: teach register coalescing about 64-bit
  i965/vec4: fix pack_uniform_registers for doubles
  i965/vec4: fix indentation in pack_uniform_registers
  i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands
  i965/vec4/nir: do not emit 64-bit MAD
  i965/vec4: do not emit 64-bit MAD
  i965/vec4: support multiple dispatch widths and groups in the IR
    builder.
  i965/vec4: Add a shuffle_64bit_data helper
  i965/vec4: Fix UBO loads for 64-bit data
  i965/vec4: Fix SSBO loads for 64-bit data
  i965/vec4: Fix SSBO stores for 64-bit data
  i965/vec4: prevent copy-propagation from values with a different type
    size
  i965/vec4: Prevent copy propagation from violating pre-gen8
    restrictions
  i965/vec4: don't propagate single-precision uniforms into 4-wide
    instructions
  i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8
    platforms
  i965/vec4: Do not use DepCtrl with 64-bit instructions
  i965/vec4: do not split scratch read/write opcodes
  i965/vec4: fix scratch offset for 64bit data
  i965/vec4: fix scratch reads for 64bit data
  i965/vec4: fix scratch writes for 64bit data
  i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit
    data
  i965/vec4: fix indentation in move_push_constants_to_pull_constants()
  i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data
  i965/vec4: make emit_pull_constant_load support 64-bit loads
  i965/vec4: fix indentation in lower_attributes_to_hw_regs()
  i965/vec4: fix attribute setup for doubles
  i965/vec4: fix store output for 64-bit types
  i965/vec4/tcs: fix input loading for 64-bit data
  i965/vec4/tcs: fix outputs for 64-bit data
  i965/vec4/tes: fix input loading for 64bit data types
  i965/vec4/tes: fix setup_payload() for 64bit data types
  i965/vec4/tes: consider register offsets during attribute setup
  i965/vec4: dump subnr for FIXED_GRF
  i965/vec4: split instructions that read 64-bit interleaved attributes
  i965/vec4/scalarize_df: do not scalarize swizzles that we can support
    natively
  i965/vec4/scalarize_df: support more swizzles via vstride=0
  i965/vec4: prevent src/dst hazards during 64-bit register allocation
  i965/vec4: run scalarize_df() after spilling
  i965/vec4: support basic spilling of 64-bit registers
  i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit
    access
  i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination
  i965/vec4: adjust spilling costs for 64-bit registers.
  i965/vec4: enable ARB_gpu_shader_fp64 for Haswell
  i965/gen7: expose OpenGL 4.0 on Haswell

Juan A. Suarez Romero (1):
  i965/vec4: handle 32 and 64 bit channels in liveness analysis

Samuel Iglesias Gonsálvez (4):
  i965/nir: double/dvec2 uniforms only need to be padded to a single
    vec4 slot
  i965/vec4: use the new helper function to create double immediates
  i965/vec4: don't copy propagate misaligned registers
  i965/vec4/gs: fix input loading for 64bit data

 src/mesa/drivers/dri/i965/brw_defines.h            |   6 +
 src/mesa/drivers/dri/i965/brw_disasm.c             |  13 +-
 src/mesa/drivers/dri/i965/brw_ir_fs.h              |  16 -
 src/mesa/drivers/dri/i965/brw_ir_vec4.h            |  47 ++
 src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp     |   3 +-
 src/mesa/drivers/dri/i965/brw_reg.h                |  24 +-
 src/mesa/drivers/dri/i965/brw_shader.cpp           |  12 +
 src/mesa/drivers/dri/i965/brw_shader.h             |  16 +
 src/mesa/drivers/dri/i965/brw_vec4.cpp             | 769 ++++++++++++++++++---
 src/mesa/drivers/dri/i965/brw_vec4.h               |  24 +
 src/mesa/drivers/dri/i965/brw_vec4_builder.h       |  39 +-
 .../drivers/dri/i965/brw_vec4_cmod_propagation.cpp |   4 +-
 .../drivers/dri/i965/brw_vec4_copy_propagation.cpp |  59 ++
 src/mesa/drivers/dri/i965/brw_vec4_cse.cpp         |  33 +-
 .../dri/i965/brw_vec4_dead_code_eliminate.cpp      |  28 +-
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp   | 104 +++
 src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp      |  51 +-
 .../drivers/dri/i965/brw_vec4_live_variables.cpp   |  32 +-
 .../drivers/dri/i965/brw_vec4_live_variables.h     |  15 +-
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp         | 611 +++++++++++++---
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp     |  85 ++-
 src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp         |  65 +-
 src/mesa/drivers/dri/i965/brw_vec4_tes.cpp         |  97 ++-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp     | 168 ++++-
 src/mesa/drivers/dri/i965/intel_extensions.c       |   5 +
 src/mesa/drivers/dri/i965/intel_screen.c           |   2 +-
 26 files changed, 1984 insertions(+), 344 deletions(-)
    

Revisions

Patches download mbox

# Name Submitter State A F R T
[Mesa-dev,01/95] i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot Iago Toral Quiroga Accepted 1
[Mesa-dev,02/95] i965/vec4/nir: simplify glsl_type_for_nir_alu_type() Iago Toral Quiroga Accepted 1
[Mesa-dev,03/95] i965/vec4/nir: allocate two registers for dvec3/dvec4 Iago Toral Quiroga New
[Mesa-dev,04/95] i965/vec4/nir: Add bit-size information to types Iago Toral Quiroga New 1
[Mesa-dev,05/95] i965/vec4/nir: support doubles in ALU operations Iago Toral Quiroga New 1
[Mesa-dev,06/95] i965/vec4/nir: fix nir_intrinsic_load_uniform for doubles Iago Toral Quiroga New
[Mesa-dev,07/95] i965/vec4/nir: set the right type for 64-bit registers Iago Toral Quiroga New
[Mesa-dev,08/95] i965/vec4/nir: fix emitting 64-bit immediates Iago Toral Quiroga Accepted
[Mesa-dev,09/95] i965/vec4: add support for printing DF immediates Iago Toral Quiroga Accepted 2
[Mesa-dev,10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis Iago Toral Quiroga New
[Mesa-dev,11/95] i965/vec4: add double/float conversion pseudo-opcodes Iago Toral Quiroga Accepted
[Mesa-dev,12/95] i965/vec4: translate d2f/f2d Iago Toral Quiroga New
[Mesa-dev,13/95] i965: add brw_vecn_grf() Iago Toral Quiroga Accepted 1
[Mesa-dev,14/95] i965/vec4: set correct register regions for 32-bit and 64-bit Iago Toral Quiroga New
[Mesa-dev,15/95] i965/disasm: align16 DF source regions have a width of 2 Iago Toral Quiroga Accepted 1
[Mesa-dev,16/95] i965/vec4: We only support 32-bit integer ALU operations for now Iago Toral Quiroga New 1
[Mesa-dev,17/95] i965/vec4: add dst_null_df() Iago Toral Quiroga Accepted 1
[Mesa-dev,18/95] i965/vec4: add VEC4_OPCODE_PICK_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga New
[Mesa-dev,19/95] i965/vec4: add VEC4_OPCODE_SET_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga New
[Mesa-dev,20/95] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT Iago Toral Quiroga New
[Mesa-dev,21/95] i965/vec4: don't copy propagate vector opcodes that operate in align1 mode Iago Toral Quiroga New
[Mesa-dev,22/95] i965/vec4: implement double unpacking Iago Toral Quiroga Accepted
[Mesa-dev,23/95] i965/vec4: implement double packing Iago Toral Quiroga Accepted
[Mesa-dev,24/95] i965/vec4/nir: implement double comparisons Iago Toral Quiroga New
[Mesa-dev,25/95] i965/vec4: fix base offset for nir_registers with doubles Iago Toral Quiroga New
[Mesa-dev,26/95] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations Iago Toral Quiroga New
[Mesa-dev,27/95] i965/vec4: make opt_vector_float ignore doubles Iago Toral Quiroga New
[Mesa-dev,28/95] i965/vec4: fix register allocation for 64-bit undef sources Iago Toral Quiroga New 1
[Mesa-dev,29/95] i965/vec4: Rename DF to/from F generator opcodes Iago Toral Quiroga New
[Mesa-dev,30/95] i965/vec4: add helpers for conversions to/from doubles Iago Toral Quiroga New
[Mesa-dev,31/95] i965/vec4: implement hardware workaround for align16 double to float conversion Iago Toral Quiroga New
[Mesa-dev,32/95] i965/vec4: implement d2i, d2u, i2d and u2d Iago Toral Quiroga New
[Mesa-dev,33/95] i965/vec4: implement d2b Iago Toral Quiroga New
[Mesa-dev,34/95] i965/vec4: implement fsign() for doubles Iago Toral Quiroga New
[Mesa-dev,35/95] i965/vec4: fix optimize predicate for doubles Iago Toral Quiroga Accepted
[Mesa-dev,36/95] i965/vec4: add a helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,37/95] i965/vec4: use the new helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,38/95] i965/vec4: allow the vec4 IR to indicate the execution size of instructions Iago Toral Quiroga New
[Mesa-dev,39/95] i965/vec4: dump the instruction execution size Iago Toral Quiroga Accepted 1
[Mesa-dev,40/95] i965/vec4: add a SIMD lowering pass Iago Toral Quiroga New
[Mesa-dev,41/95] i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions Iago Toral Quiroga New
[Mesa-dev,42/95] i965/vec4: dump NibCtrl for instructions with execsize 4 Iago Toral Quiroga New
[Mesa-dev,43/95] i965/disasm: print NibCtrl for instructions with execsize 4 Iago Toral Quiroga New
[Mesa-dev,44/95] i965/vec4: teach CSE about exec_size, group and doubles Iago Toral Quiroga New
[Mesa-dev,45/95] i965/vec4: split double-precision bcsel Iago Toral Quiroga New
[Mesa-dev,46/95] i965/vec4: add a scalarization pass for double-precision instructions Iago Toral Quiroga New
[Mesa-dev,47/95] i965/vec4: translate 64-bit swizzles to 32-bit Iago Toral Quiroga New
[Mesa-dev,48/95] i965/vec4: add a force_vstride0 flag to src_reg Iago Toral Quiroga New
[Mesa-dev,49/95] i965/vec4: implement access to DF source components Z/W Iago Toral Quiroga New
[Mesa-dev,50/95] i965/vec4: Use force_vstride0 to fix DF Z/W writes from X/Y channels Iago Toral Quiroga New
[Mesa-dev,51/95] i965/vec4: add a sanity check for force_vstride0 Iago Toral Quiroga New
[Mesa-dev,52/95] i965/vec4: print subnr in dump_instruction() Iago Toral Quiroga New
[Mesa-dev,53/95] i965/disasm: fix subreg for dst in Align16 mode Iago Toral Quiroga New 1
[Mesa-dev,54/95] i965/vec4: fix regs_read() for doubles Iago Toral Quiroga New
[Mesa-dev,55/95] i965/vec4: teach register coalescing about 64-bit Iago Toral Quiroga New
[Mesa-dev,56/95] i965/vec4: fix regs_written for doubles Iago Toral Quiroga New
[Mesa-dev,57/95] i965/vec4: fix pack_uniform_registers for doubles Iago Toral Quiroga Accepted
[Mesa-dev,58/95] i965/vec4: fix indentation in pack_uniform_registers Iago Toral Quiroga Accepted
[Mesa-dev,59/95] i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands Iago Toral Quiroga New
[Mesa-dev,60/95] i965/vec4/nir: do not emit 64-bit MAD Iago Toral Quiroga Accepted
[Mesa-dev,61/95] i965/vec4: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,62/95] i965/vec4: Add a shuffle_64bit_data helper Iago Toral Quiroga New
[Mesa-dev,63/95] i965/vec4: Fix UBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,64/95] i965/vec4: Fix SSBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,65/95] i965/vec4: Fix SSBO stores for 64-bit data Iago Toral Quiroga New
[Mesa-dev,66/95] i965/vec4: don't constant propagate 64-bit immediates Iago Toral Quiroga Accepted
[Mesa-dev,67/95] i965/vec4: prevent copy-propagation from values with a different type size Iago Toral Quiroga Accepted
[Mesa-dev,68/95] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions Iago Toral Quiroga New
[Mesa-dev,69/95] i965/vec4: don't propagate single-precision uniforms into 4-wide instructions Iago Toral Quiroga New
[Mesa-dev,70/95] i965/vec4: don't copy propagate if subnr is set Iago Toral Quiroga New
[Mesa-dev,71/95] i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms Iago Toral Quiroga New
[Mesa-dev,72/95] i965/vec4: Do not use DepCtrl with 64-bit instructions Iago Toral Quiroga New
[Mesa-dev,73/95] i965/vec4: set force_vstride0 on any 64-bit source that has subnr > 0 Iago Toral Quiroga New
[Mesa-dev,74/95] i965/vec4: do not split scratch read/write opcodes Iago Toral Quiroga New
[Mesa-dev,75/95] i965/vec4: fix scratch offset for 64bit data Iago Toral Quiroga Accepted
[Mesa-dev,76/95] i965/vec4: fix scratch reads for 64bit data Iago Toral Quiroga New
[Mesa-dev,77/95] i965/vec4: fix scratch writes for 64bit data Iago Toral Quiroga New
[Mesa-dev,78/95] i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,79/95] i965/vec4: fix indentation in move_push_constants_to_pull_constants() Iago Toral Quiroga New
[Mesa-dev,80/95] i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,81/95] i965/vec4: make emit_pull_constant_load support 64-bit loads Iago Toral Quiroga New
[Mesa-dev,82/95] i965/vec4: fix store output for 64-bit types Iago Toral Quiroga New
[Mesa-dev,83/95] i965/vec4/gs: fix input loading for 64bit data Iago Toral Quiroga New
[Mesa-dev,84/95] i965/vec4/tcs: fix input loading for 64-bit data Iago Toral Quiroga New
[Mesa-dev,85/95] i965/vec4/tcs: fix outputs for 64-bit data Iago Toral Quiroga New
[Mesa-dev,86/95] i965/vec4/tes: fix input loading for 64bit data types Iago Toral Quiroga New
[Mesa-dev,87/95] i965/vec4/tes: fix setup_payload() for 64bit data types Iago Toral Quiroga New
[Mesa-dev,88/95] i965/vec4: split instructions that read 64-bit attrs in TessEval Iago Toral Quiroga New
[Mesa-dev,89/95] i965/vec4: fix writes to Z/W:DF from a FIXED_GRF Iago Toral Quiroga New
[Mesa-dev,90/95] i965/vec4: implement force_vstride0 for FIXED_GRF Iago Toral Quiroga New
[Mesa-dev,91/95] i965/vec4: dump subnr for FIXED_GRF Iago Toral Quiroga New
[Mesa-dev,92/95] i965/vec4/scalarize_df: do not scalarize instructions with identity swizzles Iago Toral Quiroga New
[Mesa-dev,93/95] i965/vec4/scalarize_df: Always scalarize XY / ZW writemasks Iago Toral Quiroga New
[Mesa-dev,94/95] i965/vec4: enable ARB_gpu_shader_fp64 for Haswell Iago Toral Quiroga New
[Mesa-dev,95/95] i965/gen7: expose OpenGL 4.0 on Haswell Iago Toral Quiroga New
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[Mesa-dev,01/95] i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot Iago Toral Quiroga Accepted 1
[Mesa-dev,02/95] i965/vec4/nir: simplify glsl_type_for_nir_alu_type() Iago Toral Quiroga Accepted 1
[Mesa-dev,03/95] i965/vec4/nir: allocate two registers for dvec3/dvec4 Iago Toral Quiroga New
[Mesa-dev,04/95] i965/vec4/nir: Add bit-size information to types Iago Toral Quiroga New 1
[Mesa-dev,05/95] i965/vec4/nir: support doubles in ALU operations Iago Toral Quiroga New 1
[Mesa-dev,06/95] i965/vec4/nir: fix nir_intrinsic_load_uniform for doubles Iago Toral Quiroga New
[Mesa-dev,07/95] i965/vec4/nir: set the right type for 64-bit registers Iago Toral Quiroga New
[Mesa-dev,08/95] i965/vec4/nir: fix emitting 64-bit immediates Iago Toral Quiroga Accepted
[Mesa-dev,09/95] i965/vec4: add support for printing DF immediates Iago Toral Quiroga Accepted 2
[Mesa-dev,10/95] i965/vec4: handle 32 and 64 bit channels in liveness analysis Iago Toral Quiroga New
[Mesa-dev,11/95] i965/vec4: add double/float conversion pseudo-opcodes Iago Toral Quiroga Accepted
[Mesa-dev,12/95] i965/vec4: translate d2f/f2d Iago Toral Quiroga New
[Mesa-dev,13/95] i965: add brw_vecn_grf() Iago Toral Quiroga Accepted 1
[Mesa-dev,14/95] i965/vec4: set correct register regions for 32-bit and 64-bit Iago Toral Quiroga New
[Mesa-dev,15/95] i965/disasm: align16 DF source regions have a width of 2 Iago Toral Quiroga Accepted 1
[Mesa-dev,16/95] i965/vec4: We only support 32-bit integer ALU operations for now Iago Toral Quiroga New 1
[Mesa-dev,17/95] i965/vec4: add dst_null_df() Iago Toral Quiroga Accepted 1
[Mesa-dev,18/95] i965/vec4: add VEC4_OPCODE_PICK_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga New
[Mesa-dev,19/95] i965/vec4: add VEC4_OPCODE_SET_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga New
[Mesa-dev,20/95] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT Iago Toral Quiroga New
[Mesa-dev,21/95] i965/vec4: don't copy propagate vector opcodes that operate in align1 mode Iago Toral Quiroga New
[Mesa-dev,22/95] i965/vec4: implement double unpacking Iago Toral Quiroga Accepted
[Mesa-dev,23/95] i965/vec4: implement double packing Iago Toral Quiroga Accepted
[Mesa-dev,24/95] i965/vec4/nir: implement double comparisons Iago Toral Quiroga New
[Mesa-dev,25/95] i965/vec4: fix base offset for nir_registers with doubles Iago Toral Quiroga New
[Mesa-dev,26/95] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations Iago Toral Quiroga New
[Mesa-dev,27/95] i965/vec4: make opt_vector_float ignore doubles Iago Toral Quiroga New
[Mesa-dev,28/95] i965/vec4: fix register allocation for 64-bit undef sources Iago Toral Quiroga New 1
[Mesa-dev,29/95] i965/vec4: Rename DF to/from F generator opcodes Iago Toral Quiroga New
[Mesa-dev,30/95] i965/vec4: add helpers for conversions to/from doubles Iago Toral Quiroga New
[Mesa-dev,31/95] i965/vec4: implement hardware workaround for align16 double to float conversion Iago Toral Quiroga New
[Mesa-dev,32/95] i965/vec4: implement d2i, d2u, i2d and u2d Iago Toral Quiroga New
[Mesa-dev,33/95] i965/vec4: implement d2b Iago Toral Quiroga New
[Mesa-dev,34/95] i965/vec4: implement fsign() for doubles Iago Toral Quiroga New
[Mesa-dev,35/95] i965/vec4: fix optimize predicate for doubles Iago Toral Quiroga Accepted
[Mesa-dev,36/95] i965/vec4: add a helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,37/95] i965/vec4: use the new helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,38/95] i965/vec4: allow the vec4 IR to indicate the execution size of instructions Iago Toral Quiroga New
[Mesa-dev,39/95] i965/vec4: dump the instruction execution size Iago Toral Quiroga Accepted 1
[Mesa-dev,v2] i965/vec4: add a SIMD lowering pass Iago Toral Quiroga New
[Mesa-dev,41/95] i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions Iago Toral Quiroga New
[Mesa-dev,42/95] i965/vec4: dump NibCtrl for instructions with execsize 4 Iago Toral Quiroga New
[Mesa-dev,43/95] i965/disasm: print NibCtrl for instructions with execsize 4 Iago Toral Quiroga New
[Mesa-dev,44/95] i965/vec4: teach CSE about exec_size, group and doubles Iago Toral Quiroga New
[Mesa-dev,45/95] i965/vec4: split double-precision bcsel Iago Toral Quiroga New
[Mesa-dev,46/95] i965/vec4: add a scalarization pass for double-precision instructions Iago Toral Quiroga New
[Mesa-dev,47/95] i965/vec4: translate 64-bit swizzles to 32-bit Iago Toral Quiroga New
[Mesa-dev,48/95] i965/vec4: add a force_vstride0 flag to src_reg Iago Toral Quiroga New
[Mesa-dev,49/95] i965/vec4: implement access to DF source components Z/W Iago Toral Quiroga New
[Mesa-dev,50/95] i965/vec4: Use force_vstride0 to fix DF Z/W writes from X/Y channels Iago Toral Quiroga New
[Mesa-dev,51/95] i965/vec4: add a sanity check for force_vstride0 Iago Toral Quiroga New
[Mesa-dev,52/95] i965/vec4: print subnr in dump_instruction() Iago Toral Quiroga New
[Mesa-dev,53/95] i965/disasm: fix subreg for dst in Align16 mode Iago Toral Quiroga New 1
[Mesa-dev,54/95] i965/vec4: fix regs_read() for doubles Iago Toral Quiroga New
[Mesa-dev,55/95] i965/vec4: teach register coalescing about 64-bit Iago Toral Quiroga New
[Mesa-dev,56/95] i965/vec4: fix regs_written for doubles Iago Toral Quiroga New
[Mesa-dev,57/95] i965/vec4: fix pack_uniform_registers for doubles Iago Toral Quiroga Accepted
[Mesa-dev,58/95] i965/vec4: fix indentation in pack_uniform_registers Iago Toral Quiroga Accepted
[Mesa-dev,59/95] i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands Iago Toral Quiroga New
[Mesa-dev,60/95] i965/vec4/nir: do not emit 64-bit MAD Iago Toral Quiroga Accepted
[Mesa-dev,61/95] i965/vec4: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,62/95] i965/vec4: Add a shuffle_64bit_data helper Iago Toral Quiroga New
[Mesa-dev,63/95] i965/vec4: Fix UBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,64/95] i965/vec4: Fix SSBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,65/95] i965/vec4: Fix SSBO stores for 64-bit data Iago Toral Quiroga New
[Mesa-dev,66/95] i965/vec4: don't constant propagate 64-bit immediates Iago Toral Quiroga Accepted
[Mesa-dev,67/95] i965/vec4: prevent copy-propagation from values with a different type size Iago Toral Quiroga Accepted
[Mesa-dev,68/95] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions Iago Toral Quiroga New
[Mesa-dev,69/95] i965/vec4: don't propagate single-precision uniforms into 4-wide instructions Iago Toral Quiroga New
[Mesa-dev,70/95] i965/vec4: don't copy propagate if subnr is set Iago Toral Quiroga New
[Mesa-dev,71/95] i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms Iago Toral Quiroga New
[Mesa-dev,72/95] i965/vec4: Do not use DepCtrl with 64-bit instructions Iago Toral Quiroga New
[Mesa-dev,73/95] i965/vec4: set force_vstride0 on any 64-bit source that has subnr > 0 Iago Toral Quiroga New
[Mesa-dev,74/95] i965/vec4: do not split scratch read/write opcodes Iago Toral Quiroga New
[Mesa-dev,75/95] i965/vec4: fix scratch offset for 64bit data Iago Toral Quiroga Accepted
[Mesa-dev,76/95] i965/vec4: fix scratch reads for 64bit data Iago Toral Quiroga New
[Mesa-dev,77/95] i965/vec4: fix scratch writes for 64bit data Iago Toral Quiroga New
[Mesa-dev,78/95] i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,79/95] i965/vec4: fix indentation in move_push_constants_to_pull_constants() Iago Toral Quiroga New
[Mesa-dev,80/95] i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,81/95] i965/vec4: make emit_pull_constant_load support 64-bit loads Iago Toral Quiroga New
[Mesa-dev,82/95] i965/vec4: fix store output for 64-bit types Iago Toral Quiroga New
[Mesa-dev,83/95] i965/vec4/gs: fix input loading for 64bit data Iago Toral Quiroga New
[Mesa-dev,84/95] i965/vec4/tcs: fix input loading for 64-bit data Iago Toral Quiroga New
[Mesa-dev,85/95] i965/vec4/tcs: fix outputs for 64-bit data Iago Toral Quiroga New
[Mesa-dev,86/95] i965/vec4/tes: fix input loading for 64bit data types Iago Toral Quiroga New
[Mesa-dev,87/95] i965/vec4/tes: fix setup_payload() for 64bit data types Iago Toral Quiroga New
[Mesa-dev,88/95] i965/vec4: split instructions that read 64-bit attrs in TessEval Iago Toral Quiroga New
[Mesa-dev,89/95] i965/vec4: fix writes to Z/W:DF from a FIXED_GRF Iago Toral Quiroga New
[Mesa-dev,90/95] i965/vec4: implement force_vstride0 for FIXED_GRF Iago Toral Quiroga New
[Mesa-dev,91/95] i965/vec4: dump subnr for FIXED_GRF Iago Toral Quiroga New
[Mesa-dev,92/95] i965/vec4/scalarize_df: do not scalarize instructions with identity swizzles Iago Toral Quiroga New
[Mesa-dev,93/95] i965/vec4/scalarize_df: Always scalarize XY / ZW writemasks Iago Toral Quiroga New
[Mesa-dev,94/95] i965/vec4: enable ARB_gpu_shader_fp64 for Haswell Iago Toral Quiroga New
[Mesa-dev,95/95] i965/gen7: expose OpenGL 4.0 on Haswell Iago Toral Quiroga New

Patches download mbox

# Name Submitter State A F R T
[Mesa-dev,v2,001/103] i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot Iago Toral Quiroga New 1
[Mesa-dev,v2,002/103] i965/vec4/nir: simplify glsl_type_for_nir_alu_type() Iago Toral Quiroga New 1
[Mesa-dev,v2,003/103] i965/vec4/nir: allocate two registers for dvec3/dvec4 Iago Toral Quiroga New 1
[Mesa-dev,v2,004/103] i965/vec4/nir: Add bit-size information to types Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,005/103] i965/vec4/nir: support doubles in ALU operations Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,006/103] i965/vec4/nir: set the right type for 64-bit registers Iago Toral Quiroga New
[Mesa-dev,v2,007/103] i965/vec4/nir: fix emitting 64-bit immediates Iago Toral Quiroga New 1
[Mesa-dev,v2,008/103] i965/vec4: add support for printing DF immediates Iago Toral Quiroga New 1
[Mesa-dev,v2,009/103] i965/vec4: add double/float conversion pseudo-opcodes Iago Toral Quiroga New 1
[Mesa-dev,v2,010/103] i965/vec4: translate d2f/f2d Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,011/103] i965: fix subnr overflow in suboffset() Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,012/103] i965: add brw_vecn_grf() Iago Toral Quiroga New 1
[Mesa-dev,v2,013/103] i965/vec4: set correct register regions for 32-bit and 64-bit Iago Toral Quiroga New 1
[Mesa-dev,v2,014/103] i965/disasm: align16 DF source regions have a width of 2 Iago Toral Quiroga New 1
[Mesa-dev,v2,015/103] i965/vec4: We only support 32-bit integer ALU operations for now Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,016/103] i965/vec4: add dst_null_df() Iago Toral Quiroga New 1
[Mesa-dev,v2,017/103] i965/vec4: add VEC4_OPCODE_PICK_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,018/103] i965/vec4: add VEC4_OPCODE_SET_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,019/103] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,020/103] i965/vec4: don't copy propagate vector opcodes that operate in align1 mode Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,021/103] i965/vec4: implement double unpacking Iago Toral Quiroga New 1
[Mesa-dev,v2,022/103] i965/vec4: implement double packing Iago Toral Quiroga New
[Mesa-dev,v2,023/103] i965/vec4/nir: implement double comparisons Iago Toral Quiroga New
[Mesa-dev,v2,024/103] i965/vec4: fix base offset for nir_registers with doubles Iago Toral Quiroga New
[Mesa-dev,v2,025/103] i965/vec4: fix indentation in get_nir_src() Iago Toral Quiroga Accepted
[Mesa-dev,v2,026/103] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations Iago Toral Quiroga New
[Mesa-dev,v2,027/103] i965/vec4: make opt_vector_float ignore doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,028/103] i965/vec4: fix register allocation for 64-bit undef sources Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,029/103] i965/vec4: Rename DF to/from F generator opcodes Iago Toral Quiroga New
[Mesa-dev,v2,030/103] i965/vec4: add helpers for conversions to/from doubles Iago Toral Quiroga New
[Mesa-dev,v2,031/103] i965/vec4: implement hardware workaround for align16 double to float conver... Iago Toral Quiroga New
[Mesa-dev,v2,032/103] i965/vec4: implement d2i, d2u, i2d and u2d Iago Toral Quiroga New
[Mesa-dev,v2,033/103] i965/vec4: implement d2b Iago Toral Quiroga New
[Mesa-dev,v2,034/103] i965/vec4: implement fsign() for doubles Iago Toral Quiroga New
[Mesa-dev,v2,035/103] i965/vec4: fix optimize predicate for doubles Iago Toral Quiroga New
[Mesa-dev,v2,036/103] i965/vec4: add a helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,v2,037/103] i965/vec4: use the new helper function to create double immediates Iago Toral Quiroga Accepted
[Mesa-dev,v2,038/103] i965: move exec_size from fs_instruction to backend_instruction Iago Toral Quiroga Accepted
[Mesa-dev,v2,039/103] i965/vec4: fix size_written for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,040/103] i965/vec4: fix regs_read() for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,041/103] i965/vec4: use the IR's execution size Iago Toral Quiroga Accepted
[Mesa-dev,v2,042/103] i965/vec4: dump the instruction execution size Iago Toral Quiroga New 1
[Mesa-dev,v2,043/103] i965/vec4: handle 32 and 64 bit channels in liveness analysis Iago Toral Quiroga New
[Mesa-dev,v2,044/103] i965/vec4: add a horiz_offset() helper Iago Toral Quiroga New
[Mesa-dev,v2,045/103] i965: move the group field from fs_inst to backend_instruction. Iago Toral Quiroga Accepted
[Mesa-dev,v2,046/103] i965/vec4: add a SIMD lowering pass Iago Toral Quiroga New
[Mesa-dev,v2,047/103] i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions Iago Toral Quiroga Accepted
[Mesa-dev,v2,048/103] i965/vec4: dump NibCtrl for instructions with execsize != 8 Iago Toral Quiroga Accepted
[Mesa-dev,v2,049/103] i965/disasm: print NibCtrl for instructions with execsize < 8 Iago Toral Quiroga Accepted
[Mesa-dev,v2,050/103] i965/vec4: teach CSE about exec_size, group and doubles Iago Toral Quiroga New
[Mesa-dev,v2,051/103] i965/vec4: teach cmod propagation about different execution sizes Iago Toral Quiroga Accepted
[Mesa-dev,v2,052/103] i965/vec4: split double-precision bcsel Iago Toral Quiroga New
[Mesa-dev,v2,053/103] i965/vec4: add a scalarization pass for double-precision instructions Iago Toral Quiroga New
[Mesa-dev,v2,054/103] i965/vec4: translate 64-bit swizzles to 32-bit Iago Toral Quiroga New
[Mesa-dev,v2,055/103] i965/vec4: implement access to DF source components Z/W Iago Toral Quiroga Accepted
[Mesa-dev,v2,056/103] i965/disasm: fix subreg for dst in Align16 mode Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,057/103] i965/vec4: teach register coalescing about 64-bit Iago Toral Quiroga New
[Mesa-dev,v2,058/103] i965/vec4: fix pack_uniform_registers for doubles Iago Toral Quiroga New
[Mesa-dev,v2,059/103] i965/vec4: fix indentation in pack_uniform_registers Iago Toral Quiroga New
[Mesa-dev,v2,060/103] i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands Iago Toral Quiroga New
[Mesa-dev,v2,061/103] i965/vec4/nir: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,v2,062/103] i965/vec4: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,v2,063/103] i965/vec4: support multiple dispatch widths and groups in the IR builder. Iago Toral Quiroga Accepted
[Mesa-dev,v2,064/103] i965/vec4: Add a shuffle_64bit_data helper Iago Toral Quiroga New
[Mesa-dev,v2,065/103] i965/vec4: Fix UBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,066/103] i965/vec4: Fix SSBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,067/103] i965/vec4: Fix SSBO stores for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,068/103] i965/vec4: don't constant propagate 64-bit immediates Iago Toral Quiroga New
[Mesa-dev,v2,069/103] i965/vec4: prevent copy-propagation from values with a different type size Iago Toral Quiroga New
[Mesa-dev,v2,070/103] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions Iago Toral Quiroga Accepted
[Mesa-dev,v2,071/103] i965/vec4: don't propagate single-precision uniforms into 4-wide instructions Iago Toral Quiroga Accepted
[Mesa-dev,v2,072/103] i965/vec4: don't copy propagate misaligned registers Iago Toral Quiroga Accepted
[Mesa-dev,v2,073/103] i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms Iago Toral Quiroga New
[Mesa-dev,v2,074/103] i965/vec4: Do not use DepCtrl with 64-bit instructions Iago Toral Quiroga New
[Mesa-dev,v2,075/103] i965/vec4: do not split scratch read/write opcodes Iago Toral Quiroga Accepted
[Mesa-dev,v2,076/103] i965/vec4: fix scratch offset for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,077/103] i965/vec4: fix scratch reads for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,078/103] i965/vec4: fix scratch writes for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,079/103] i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,080/103] i965/vec4: fix indentation in move_push_constants_to_pull_constants() Iago Toral Quiroga Accepted
[Mesa-dev,v2,081/103] i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,082/103] i965/vec4: make emit_pull_constant_load support 64-bit loads Iago Toral Quiroga New
[Mesa-dev,v2,083/103] i965/vec4: fix indentation in lower_attributes_to_hw_regs() Iago Toral Quiroga Accepted
[Mesa-dev,v2,084/103] i965/vec4: fix attribute setup for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,085/103] i965/vec4: fix store output for 64-bit types Iago Toral Quiroga New
[Mesa-dev,v2,086/103] i965/vec4/gs: fix input loading for 64bit data Iago Toral Quiroga Accepted
[Mesa-dev,v2,087/103] i965/vec4/tcs: fix input loading for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,088/103] i965/vec4/tcs: fix outputs for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,089/103] i965/vec4/tes: fix input loading for 64bit data types Iago Toral Quiroga New
[Mesa-dev,v2,090/103] i965/vec4/tes: fix setup_payload() for 64bit data types Iago Toral Quiroga Accepted
[Mesa-dev,v2,091/103] i965/vec4/tes: consider register offsets during attribute setup Iago Toral Quiroga Accepted
[Mesa-dev,v2,092/103] i965/vec4: dump subnr for FIXED_GRF Iago Toral Quiroga Accepted
[Mesa-dev,v2,093/103] i965/vec4: split instructions that read 64-bit interleaved attributes Iago Toral Quiroga New
[Mesa-dev,v2,094/103] i965/vec4/scalarize_df: do not scalarize swizzles that we can support natively Iago Toral Quiroga New
[Mesa-dev,v2,095/103] i965/vec4/scalarize_df: support more swizzles via vstride=0 Iago Toral Quiroga New
[Mesa-dev,v2,096/103] i965/vec4: prevent src/dst hazards during 64-bit register allocation Iago Toral Quiroga Accepted
[Mesa-dev,v2,097/103] i965/vec4: run scalarize_df() after spilling Iago Toral Quiroga New
[Mesa-dev,v2,098/103] i965/vec4: support basic spilling of 64-bit registers Iago Toral Quiroga New
[Mesa-dev,v2,099/103] i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit access Iago Toral Quiroga Accepted
[Mesa-dev,v2,100/103] i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination Iago Toral Quiroga New
[Mesa-dev,v2,101/103] i965/vec4: adjust spilling costs for 64-bit registers. Iago Toral Quiroga New
[Mesa-dev,v2,102/103] i965/vec4: enable ARB_gpu_shader_fp64 for Haswell Iago Toral Quiroga Accepted
[Mesa-dev,v2,103/103] i965/gen7: expose OpenGL 4.0 on Haswell Iago Toral Quiroga New
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[Mesa-dev,v2,001/103] i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot Iago Toral Quiroga New 1
[Mesa-dev,v2,002/103] i965/vec4/nir: simplify glsl_type_for_nir_alu_type() Iago Toral Quiroga New 1
[Mesa-dev,v2,003/103] i965/vec4/nir: allocate two registers for dvec3/dvec4 Iago Toral Quiroga New 1
[Mesa-dev,v2,004/103] i965/vec4/nir: Add bit-size information to types Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,005/103] i965/vec4/nir: support doubles in ALU operations Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,006/103] i965/vec4/nir: set the right type for 64-bit registers Iago Toral Quiroga New
[Mesa-dev,v2,007/103] i965/vec4/nir: fix emitting 64-bit immediates Iago Toral Quiroga New 1
[Mesa-dev,v2,008/103] i965/vec4: add support for printing DF immediates Iago Toral Quiroga New 1
[Mesa-dev,v2,009/103] i965/vec4: add double/float conversion pseudo-opcodes Iago Toral Quiroga New 1
[Mesa-dev,v2,010/103] i965/vec4: translate d2f/f2d Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,011/103] i965: fix subnr overflow in suboffset() Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,012/103] i965: add brw_vecn_grf() Iago Toral Quiroga New 1
[Mesa-dev,v2,013/103] i965/vec4: set correct register regions for 32-bit and 64-bit Iago Toral Quiroga New 1
[Mesa-dev,v2,014/103] i965/disasm: align16 DF source regions have a width of 2 Iago Toral Quiroga New 1
[Mesa-dev,v2,015/103] i965/vec4: We only support 32-bit integer ALU operations for now Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,016/103] i965/vec4: add dst_null_df() Iago Toral Quiroga New 1
[Mesa-dev,v2,017/103] i965/vec4: add VEC4_OPCODE_PICK_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,018/103] i965/vec4: add VEC4_OPCODE_SET_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,019/103] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,020/103] i965/vec4: don't copy propagate vector opcodes that operate in align1 mode Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,021/103] i965/vec4: implement double unpacking Iago Toral Quiroga New 1
[Mesa-dev,v2,022/103] i965/vec4: implement double packing Iago Toral Quiroga New
[Mesa-dev,v2,023/103] i965/vec4/nir: implement double comparisons Iago Toral Quiroga New
[Mesa-dev,v2,024/103] i965/vec4: fix base offset for nir_registers with doubles Iago Toral Quiroga New
[Mesa-dev,v2,025/103] i965/vec4: fix indentation in get_nir_src() Iago Toral Quiroga Accepted
[Mesa-dev,v2,026/103] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations Iago Toral Quiroga New
[Mesa-dev,v2,027/103] i965/vec4: make opt_vector_float ignore doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,028/103] i965/vec4: fix register allocation for 64-bit undef sources Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,029/103] i965/vec4: Rename DF to/from F generator opcodes Iago Toral Quiroga New
[Mesa-dev,v2,030/103] i965/vec4: add helpers for conversions to/from doubles Iago Toral Quiroga New
[Mesa-dev,v2,031/103] i965/vec4: implement hardware workaround for align16 double to float conver... Iago Toral Quiroga New
[Mesa-dev,v2,032/103] i965/vec4: implement d2i, d2u, i2d and u2d Iago Toral Quiroga New
[Mesa-dev,v2,033/103] i965/vec4: implement d2b Iago Toral Quiroga New
[Mesa-dev,v2,034/103] i965/vec4: implement fsign() for doubles Iago Toral Quiroga New
[Mesa-dev,v2,035/103] i965/vec4: fix optimize predicate for doubles Iago Toral Quiroga New
[Mesa-dev,v2,036/103] i965/vec4: add a helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,v2,037/103] i965/vec4: use the new helper function to create double immediates Iago Toral Quiroga Accepted
[Mesa-dev,v2,038/103] i965: move exec_size from fs_instruction to backend_instruction Iago Toral Quiroga Accepted
[Mesa-dev,v2,039/103] i965/vec4: fix size_written for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,040/103] i965/vec4: fix regs_read() for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,041/103] i965/vec4: use the IR's execution size Iago Toral Quiroga Accepted
[Mesa-dev,v2,042/103] i965/vec4: dump the instruction execution size Iago Toral Quiroga New 1
[Mesa-dev,v2,043/103] i965/vec4: handle 32 and 64 bit channels in liveness analysis Iago Toral Quiroga New
[Mesa-dev,v2,044/103] i965/vec4: add a horiz_offset() helper Iago Toral Quiroga New
[Mesa-dev,v2,045/103] i965: move the group field from fs_inst to backend_instruction. Iago Toral Quiroga Accepted
[Mesa-dev,v2,046/103] i965/vec4: add a SIMD lowering pass Iago Toral Quiroga New
[Mesa-dev,v2,047/103] i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions Iago Toral Quiroga Accepted
[Mesa-dev,v2,048/103] i965/vec4: dump NibCtrl for instructions with execsize != 8 Iago Toral Quiroga Accepted
[Mesa-dev,v2,049/103] i965/disasm: print NibCtrl for instructions with execsize < 8 Iago Toral Quiroga Accepted
[Mesa-dev,v2,050/103] i965/vec4: teach CSE about exec_size, group and doubles Iago Toral Quiroga New
[Mesa-dev,v2,051/103] i965/vec4: teach cmod propagation about different execution sizes Iago Toral Quiroga Accepted
[Mesa-dev,v2,052/103] i965/vec4: split double-precision bcsel Iago Toral Quiroga New
[Mesa-dev,v2,053/103] i965/vec4: add a scalarization pass for double-precision instructions Iago Toral Quiroga New
[Mesa-dev,v2,054/103] i965/vec4: translate 64-bit swizzles to 32-bit Iago Toral Quiroga New
[Mesa-dev,v2,055/103] i965/vec4: implement access to DF source components Z/W Iago Toral Quiroga Accepted
[Mesa-dev,v2,056/103] i965/disasm: fix subreg for dst in Align16 mode Iago Toral Quiroga Accepted 1
[Mesa-dev,v2.1] i965/vec4: teach register coalescing about 64-bit Iago Toral Quiroga Accepted
[Mesa-dev,v2,058/103] i965/vec4: fix pack_uniform_registers for doubles Iago Toral Quiroga New
[Mesa-dev,v2,059/103] i965/vec4: fix indentation in pack_uniform_registers Iago Toral Quiroga New
[Mesa-dev,v2,060/103] i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands Iago Toral Quiroga New
[Mesa-dev,v2,061/103] i965/vec4/nir: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,v2,062/103] i965/vec4: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,v2,063/103] i965/vec4: support multiple dispatch widths and groups in the IR builder. Iago Toral Quiroga Accepted
[Mesa-dev,v2,064/103] i965/vec4: Add a shuffle_64bit_data helper Iago Toral Quiroga New
[Mesa-dev,v2,065/103] i965/vec4: Fix UBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,066/103] i965/vec4: Fix SSBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,067/103] i965/vec4: Fix SSBO stores for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,068/103] i965/vec4: don't constant propagate 64-bit immediates Iago Toral Quiroga New
[Mesa-dev,v2,069/103] i965/vec4: prevent copy-propagation from values with a different type size Iago Toral Quiroga New
[Mesa-dev,v2,070/103] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions Iago Toral Quiroga Accepted
[Mesa-dev,v2,071/103] i965/vec4: don't propagate single-precision uniforms into 4-wide instructions Iago Toral Quiroga Accepted
[Mesa-dev,v2,072/103] i965/vec4: don't copy propagate misaligned registers Iago Toral Quiroga Accepted
[Mesa-dev,v2,073/103] i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms Iago Toral Quiroga New
[Mesa-dev,v2,074/103] i965/vec4: Do not use DepCtrl with 64-bit instructions Iago Toral Quiroga New
[Mesa-dev,v2,075/103] i965/vec4: do not split scratch read/write opcodes Iago Toral Quiroga Accepted
[Mesa-dev,v2,076/103] i965/vec4: fix scratch offset for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,077/103] i965/vec4: fix scratch reads for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,078/103] i965/vec4: fix scratch writes for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,079/103] i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,080/103] i965/vec4: fix indentation in move_push_constants_to_pull_constants() Iago Toral Quiroga Accepted
[Mesa-dev,v2,081/103] i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,082/103] i965/vec4: make emit_pull_constant_load support 64-bit loads Iago Toral Quiroga New
[Mesa-dev,v2,083/103] i965/vec4: fix indentation in lower_attributes_to_hw_regs() Iago Toral Quiroga Accepted
[Mesa-dev,v2,084/103] i965/vec4: fix attribute setup for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,085/103] i965/vec4: fix store output for 64-bit types Iago Toral Quiroga New
[Mesa-dev,v2,086/103] i965/vec4/gs: fix input loading for 64bit data Iago Toral Quiroga Accepted
[Mesa-dev,v2,087/103] i965/vec4/tcs: fix input loading for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,088/103] i965/vec4/tcs: fix outputs for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,089/103] i965/vec4/tes: fix input loading for 64bit data types Iago Toral Quiroga New
[Mesa-dev,v2,090/103] i965/vec4/tes: fix setup_payload() for 64bit data types Iago Toral Quiroga Accepted
[Mesa-dev,v2,091/103] i965/vec4/tes: consider register offsets during attribute setup Iago Toral Quiroga Accepted
[Mesa-dev,v2,092/103] i965/vec4: dump subnr for FIXED_GRF Iago Toral Quiroga Accepted
[Mesa-dev,v2,093/103] i965/vec4: split instructions that read 64-bit interleaved attributes Iago Toral Quiroga New
[Mesa-dev,v2,094/103] i965/vec4/scalarize_df: do not scalarize swizzles that we can support natively Iago Toral Quiroga New
[Mesa-dev,v2,095/103] i965/vec4/scalarize_df: support more swizzles via vstride=0 Iago Toral Quiroga New
[Mesa-dev,v2,096/103] i965/vec4: prevent src/dst hazards during 64-bit register allocation Iago Toral Quiroga Accepted
[Mesa-dev,v2,097/103] i965/vec4: run scalarize_df() after spilling Iago Toral Quiroga New
[Mesa-dev,v2,098/103] i965/vec4: support basic spilling of 64-bit registers Iago Toral Quiroga New
[Mesa-dev,v2,099/103] i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit access Iago Toral Quiroga Accepted
[Mesa-dev,v2,100/103] i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination Iago Toral Quiroga New
[Mesa-dev,v2,101/103] i965/vec4: adjust spilling costs for 64-bit registers. Iago Toral Quiroga New
[Mesa-dev,v2,102/103] i965/vec4: enable ARB_gpu_shader_fp64 for Haswell Iago Toral Quiroga Accepted
[Mesa-dev,v2,103/103] i965/gen7: expose OpenGL 4.0 on Haswell Iago Toral Quiroga New
SERIES REVISION LOOKS STRANGE. Please double-check patch list and the ordering before proceeding.

Patches download mbox

# Name Submitter State A F R T
[Mesa-dev,v2,001/103] i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot Iago Toral Quiroga New 1
[Mesa-dev,v2,002/103] i965/vec4/nir: simplify glsl_type_for_nir_alu_type() Iago Toral Quiroga New 1
[Mesa-dev,v2,003/103] i965/vec4/nir: allocate two registers for dvec3/dvec4 Iago Toral Quiroga New 1
[Mesa-dev,v2,004/103] i965/vec4/nir: Add bit-size information to types Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,005/103] i965/vec4/nir: support doubles in ALU operations Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,006/103] i965/vec4/nir: set the right type for 64-bit registers Iago Toral Quiroga New
[Mesa-dev,v2,007/103] i965/vec4/nir: fix emitting 64-bit immediates Iago Toral Quiroga New 1
[Mesa-dev,v2,008/103] i965/vec4: add support for printing DF immediates Iago Toral Quiroga New 1
[Mesa-dev,v2,009/103] i965/vec4: add double/float conversion pseudo-opcodes Iago Toral Quiroga New 1
[Mesa-dev,v2,010/103] i965/vec4: translate d2f/f2d Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,011/103] i965: fix subnr overflow in suboffset() Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,012/103] i965: add brw_vecn_grf() Iago Toral Quiroga New 1
[Mesa-dev,v2,013/103] i965/vec4: set correct register regions for 32-bit and 64-bit Iago Toral Quiroga New 1
[Mesa-dev,v2,014/103] i965/disasm: align16 DF source regions have a width of 2 Iago Toral Quiroga New 1
[Mesa-dev,v2,015/103] i965/vec4: We only support 32-bit integer ALU operations for now Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,016/103] i965/vec4: add dst_null_df() Iago Toral Quiroga New 1
[Mesa-dev,v2,017/103] i965/vec4: add VEC4_OPCODE_PICK_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,018/103] i965/vec4: add VEC4_OPCODE_SET_{LOW, HIGH}_32BIT opcodes Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,019/103] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,020/103] i965/vec4: don't copy propagate vector opcodes that operate in align1 mode Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,021/103] i965/vec4: implement double unpacking Iago Toral Quiroga New 1
[Mesa-dev,v2,022/103] i965/vec4: implement double packing Iago Toral Quiroga New
[Mesa-dev,v2,023/103] i965/vec4/nir: implement double comparisons Iago Toral Quiroga New
[Mesa-dev,v2,024/103] i965/vec4: fix base offset for nir_registers with doubles Iago Toral Quiroga New
[Mesa-dev,v2,025/103] i965/vec4: fix indentation in get_nir_src() Iago Toral Quiroga Accepted
[Mesa-dev,v2,026/103] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations Iago Toral Quiroga New
[Mesa-dev,v2,027/103] i965/vec4: make opt_vector_float ignore doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,028/103] i965/vec4: fix register allocation for 64-bit undef sources Iago Toral Quiroga Accepted 1
[Mesa-dev,v2,029/103] i965/vec4: Rename DF to/from F generator opcodes Iago Toral Quiroga New
[Mesa-dev,v2,030/103] i965/vec4: add helpers for conversions to/from doubles Iago Toral Quiroga New
[Mesa-dev,v2,031/103] i965/vec4: implement hardware workaround for align16 double to float conver... Iago Toral Quiroga New
[Mesa-dev,v2,032/103] i965/vec4: implement d2i, d2u, i2d and u2d Iago Toral Quiroga New
[Mesa-dev,v2,033/103] i965/vec4: implement d2b Iago Toral Quiroga New
[Mesa-dev,v2,034/103] i965/vec4: implement fsign() for doubles Iago Toral Quiroga New
[Mesa-dev,v2,035/103] i965/vec4: fix optimize predicate for doubles Iago Toral Quiroga New
[Mesa-dev,v2,036/103] i965/vec4: add a helper function to create double immediates Iago Toral Quiroga New
[Mesa-dev,v2,037/103] i965/vec4: use the new helper function to create double immediates Iago Toral Quiroga Accepted
[Mesa-dev,v2,038/103] i965: move exec_size from fs_instruction to backend_instruction Iago Toral Quiroga Accepted
[Mesa-dev,v2,039/103] i965/vec4: fix size_written for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,040/103] i965/vec4: fix regs_read() for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,041/103] i965/vec4: use the IR's execution size Iago Toral Quiroga Accepted
[Mesa-dev,v2,042/103] i965/vec4: dump the instruction execution size Iago Toral Quiroga New 1
[Mesa-dev,v2,043/103] i965/vec4: handle 32 and 64 bit channels in liveness analysis Iago Toral Quiroga New
[Mesa-dev,v2,044/103] i965/vec4: add a horiz_offset() helper Iago Toral Quiroga New
[Mesa-dev,v2,045/103] i965: move the group field from fs_inst to backend_instruction. Iago Toral Quiroga Accepted
[Mesa-dev,v2,046/103] i965/vec4: add a SIMD lowering pass Iago Toral Quiroga New
[Mesa-dev,v2,047/103] i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions Iago Toral Quiroga Accepted
[Mesa-dev,v2,048/103] i965/vec4: dump NibCtrl for instructions with execsize != 8 Iago Toral Quiroga Accepted
[Mesa-dev,v2,049/103] i965/disasm: print NibCtrl for instructions with execsize < 8 Iago Toral Quiroga Accepted
[Mesa-dev,v2,050/103] i965/vec4: teach CSE about exec_size, group and doubles Iago Toral Quiroga New
[Mesa-dev,v2,051/103] i965/vec4: teach cmod propagation about different execution sizes Iago Toral Quiroga Accepted
[Mesa-dev,v2,052/103] i965/vec4: split double-precision bcsel Iago Toral Quiroga New
[Mesa-dev,v2,053/103] i965/vec4: add a scalarization pass for double-precision instructions Iago Toral Quiroga New
[Mesa-dev,v2,054/103] i965/vec4: translate 64-bit swizzles to 32-bit Iago Toral Quiroga New
[Mesa-dev,v2,055/103] i965/vec4: implement access to DF source components Z/W Iago Toral Quiroga Accepted
[Mesa-dev,v2,056/103] i965/disasm: fix subreg for dst in Align16 mode Iago Toral Quiroga Accepted 1
[Mesa-dev,v2.1] i965/vec4: teach register coalescing about 64-bit Iago Toral Quiroga Accepted
[Mesa-dev,v2,058/103] i965/vec4: fix pack_uniform_registers for doubles Iago Toral Quiroga New
[Mesa-dev,v2,059/103] i965/vec4: fix indentation in pack_uniform_registers Iago Toral Quiroga New
[Mesa-dev,v2,060/103] i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands Iago Toral Quiroga New
[Mesa-dev,v2,061/103] i965/vec4/nir: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,v2,062/103] i965/vec4: do not emit 64-bit MAD Iago Toral Quiroga New
[Mesa-dev,v2,063/103] i965/vec4: support multiple dispatch widths and groups in the IR builder. Iago Toral Quiroga Accepted
[Mesa-dev,v2,064/103] i965/vec4: Add a shuffle_64bit_data helper Iago Toral Quiroga New
[Mesa-dev,v2,065/103] i965/vec4: Fix UBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,066/103] i965/vec4: Fix SSBO loads for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,067/103] i965/vec4: Fix SSBO stores for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,068/103] i965/vec4: don't constant propagate 64-bit immediates Iago Toral Quiroga New
[Mesa-dev,v2,069/103] i965/vec4: prevent copy-propagation from values with a different type size Iago Toral Quiroga New
[Mesa-dev,v2,070/103] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions Iago Toral Quiroga Accepted
[Mesa-dev,v2,071/103] i965/vec4: don't propagate single-precision uniforms into 4-wide instructions Iago Toral Quiroga Accepted
[Mesa-dev,v2,072/103] i965/vec4: don't copy propagate misaligned registers Iago Toral Quiroga Accepted
[Mesa-dev,v2,073/103] i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platforms Iago Toral Quiroga New
[Mesa-dev,v2,074/103] i965/vec4: Do not use DepCtrl with 64-bit instructions Iago Toral Quiroga New
[Mesa-dev,v2,075/103] i965/vec4: do not split scratch read/write opcodes Iago Toral Quiroga Accepted
[Mesa-dev,v2,076/103] i965/vec4: fix scratch offset for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,077/103] i965/vec4: fix scratch reads for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,078/103] i965/vec4: fix scratch writes for 64bit data Iago Toral Quiroga New
[Mesa-dev,v2,079/103] i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,080/103] i965/vec4: fix indentation in move_push_constants_to_pull_constants() Iago Toral Quiroga Accepted
[Mesa-dev,v2,081/103] i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,082/103] i965/vec4: make emit_pull_constant_load support 64-bit loads Iago Toral Quiroga New
[Mesa-dev,v2,083/103] i965/vec4: fix indentation in lower_attributes_to_hw_regs() Iago Toral Quiroga Accepted
[Mesa-dev,v2,084/103] i965/vec4: fix attribute setup for doubles Iago Toral Quiroga Accepted
[Mesa-dev,v2,085/103] i965/vec4: fix store output for 64-bit types Iago Toral Quiroga New
[Mesa-dev,v2,086/103] i965/vec4/gs: fix input loading for 64bit data Iago Toral Quiroga Accepted
[Mesa-dev,v2,087/103] i965/vec4/tcs: fix input loading for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,088/103] i965/vec4/tcs: fix outputs for 64-bit data Iago Toral Quiroga New
[Mesa-dev,v2,089/103] i965/vec4/tes: fix input loading for 64bit data types Iago Toral Quiroga New
[Mesa-dev,v2,090/103] i965/vec4/tes: fix setup_payload() for 64bit data types Iago Toral Quiroga Accepted
[Mesa-dev,v2,091/103] i965/vec4/tes: consider register offsets during attribute setup Iago Toral Quiroga Accepted
[Mesa-dev,v2,092/103] i965/vec4: dump subnr for FIXED_GRF Iago Toral Quiroga Accepted
[Mesa-dev,v2,093/103] i965/vec4: split instructions that read 64-bit interleaved attributes Iago Toral Quiroga New
[Mesa-dev,v2,094/103] i965/vec4/scalarize_df: do not scalarize swizzles that we can support natively Iago Toral Quiroga New
[Mesa-dev,v2,095/103] i965/vec4/scalarize_df: support more swizzles via vstride=0 Iago Toral Quiroga New
[Mesa-dev,v2,096/103] i965/vec4: prevent src/dst hazards during 64-bit register allocation Iago Toral Quiroga Accepted
[Mesa-dev,v2,097/103] i965/vec4: run scalarize_df() after spilling Iago Toral Quiroga New
[Mesa-dev,v2,098/103] i965/vec4: support basic spilling of 64-bit registers Iago Toral Quiroga New
[Mesa-dev,v2,099/103] i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit access Iago Toral Quiroga Accepted
[Mesa-dev,v2,100/103] i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination Iago Toral Quiroga New
[Mesa-dev,v2,101/103] i965/vec4: adjust spilling costs for 64-bit registers. Iago Toral Quiroga New
[Mesa-dev,v2,102/103] i965/vec4: enable ARB_gpu_shader_fp64 for Haswell Iago Toral Quiroga Accepted
[Mesa-dev,v2.1] i965/gen7: expose OpenGL 4.0 on Haswell Iago Toral Quiroga New 1