Patches

Show patches with: Submitter = Iago Toral Quiroga       |    Archived = No   
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Patch A F R T Date Submitter Delegate State
[v2,01/53] compiler/nir: add a nir_b2f() helper 2018-12-19 Iago Toral Quiroga New
[v2,02/53] compiler/nir: add nir_fadd_imm() and nir_fadd_imm() helpers 2018-12-19 Iago Toral Quiroga New
[v2,03/53] compiler/spirv: handle 16-bit float in radians() and degrees() 1 2018-12-19 Iago Toral Quiroga Accepted
[v2,04/53] compiler/spirv: implement 16-bit asin 2018-12-19 Iago Toral Quiroga New
[v2,05/53] compiler/spirv: implement 16-bit acos 2018-12-19 Iago Toral Quiroga New
[v2,06/53] compiler/spirv: implement 16-bit atan 2018-12-19 Iago Toral Quiroga Accepted
[v2,07/53] compiler/spirv: implement 16-bit atan2 2018-12-19 Iago Toral Quiroga Accepted
[v2,08/53] compiler/spirv: implement 16-bit exp and log 1 2018-12-19 Iago Toral Quiroga Accepted
[v2,09/53] compiler/spirv: implement 16-bit hyperbolic trigonometric functions 2018-12-19 Iago Toral Quiroga New
[v2,10/53] compiler/spirv: implement 16-bit frexp 1 2018-12-19 Iago Toral Quiroga New
[v2,11/53] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin() 1 2018-12-19 Iago Toral Quiroga Accepted
[v2,12/53] intel/compiler: add a NIR pass to lower conversions 1 2018-12-19 Iago Toral Quiroga New
[v2,13/53] intel/compiler: add a helper to handle conversions to 64-bit in atom 1 2018-12-19 Iago Toral Quiroga New
[v2,14/53] intel/compiler: split float to 64-bit opcodes from int to 64-bit 1 2018-12-19 Iago Toral Quiroga New
[v2,15/53] intel/compiler: handle b2i/b2f with other integer conversion opcodes 2 2018-12-19 Iago Toral Quiroga New
[v2,16/53] intel/compiler: handle conversions to half-float 1 2018-12-19 Iago Toral Quiroga Accepted
[v2,17/53] intel/compiler: lower some 16-bit float operations to 32-bit 2 2018-12-19 Iago Toral Quiroga New
[v2,18/53] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 1 2018-12-19 Iago Toral Quiroga New
[v2,19/53] intel/compiler: implement 16-bit fsign 1 2018-12-19 Iago Toral Quiroga New
[v2,20/53] intel/compiler: allow extended math functions with HF operands 1 2018-12-19 Iago Toral Quiroga New
[v2,21/53] compiler/nir: add lowering option for 16-bit fmod 1 2018-12-19 Iago Toral Quiroga New
[v2,22/53] intel/compiler: lower 16-bit fmod 1 2018-12-19 Iago Toral Quiroga New
[v2,23/53] compiler/nir: add lowering for 16-bit flrp 1 2018-12-19 Iago Toral Quiroga New
[v2,24/53] intel/compiler: lower 16-bit flrp 1 2018-12-19 Iago Toral Quiroga New
[v2,25/53] compiler/nir: add lowering for 16-bit ldexp 2 2018-12-19 Iago Toral Quiroga Accepted
[v2,26/53] intel/compiler: Extended Math is limited to SIMD8 on half-float 1 2018-12-19 Iago Toral Quiroga New
[v2,27/53] intel/compiler: add instruction setters for Src1Type and Src2Type. 1 2018-12-19 Iago Toral Quiroga New
[v2,28/53] intel/compiler: add new half-float register type for 3-src instructions 1 2018-12-19 Iago Toral Quiroga New
[v2,29/53] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits 1 2018-12-19 Iago Toral Quiroga New
[v2,30/53] intel/compiler: allow half-float on 3-source instructions since gen8 1 2018-12-19 Iago Toral Quiroga New
[v2,31/53] intel/compiler: set correct precision fields for 3-source float instructions 1 2018-12-19 Iago Toral Quiroga New
[v2,32/53] intel/compiler: don't propagate HF immediates to 3-src instructions 1 2018-12-19 Iago Toral Quiroga New
[v2,33/53] intel/compiler: fix ddx and ddy for 16-bit float 1 2018-12-19 Iago Toral Quiroga Accepted
[v2,34/53] intel/compiler: fix ddy for half-float in gen8 1 2018-12-19 Iago Toral Quiroga New
[v2,35/53] intel/compiler: workaround for SIMD8 half-float MAD in gen < 9 1 2018-12-19 Iago Toral Quiroga New
[v2,36/53] intel/compiler: split is_partial_write() into two variants 2018-12-19 Iago Toral Quiroga New
[v2,37/53] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit 1 2018-12-19 Iago Toral Quiroga New
[v2,38/53] intel/compiler: handle 64-bit to 8-bit conversions 2018-12-19 Iago Toral Quiroga New
[v2,39/53] intel/compiler: add a helper to do conversions between integer and half-float 1 2018-12-19 Iago Toral Quiroga New
[v2,40/53] intel/compiler: handle conversions between int and half-float on atom 1 2018-12-19 Iago Toral Quiroga New
[v2,41/53] intel/compiler: assert that lower conversions produces valid strides 1 2018-12-19 Iago Toral Quiroga New
[v2,42/53] intel/compiler: implement isign for int8 1 2018-12-19 Iago Toral Quiroga New
[v2,43/53] intel/eu: force stride of 2 on NULL register for Byte instructions 1 2018-12-19 Iago Toral Quiroga New
[v2,44/53] compiler/spirv: add support for Float16 and Int8 capabilities 1 2018-12-19 Iago Toral Quiroga New
[v2,45/53] anv/pipeline: support Float16 and Int8 capabilities in gen8+ 1 2018-12-19 Iago Toral Quiroga New
[v2,46/53] anv/device: expose shaderFloat16 and shaderInt8 in gen8+ 1 2018-12-19 Iago Toral Quiroga New
[v2,47/53] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit 2018-12-19 Iago Toral Quiroga Accepted
[v2,48/53] intel/compiler: add a brw_reg_type_is_integer helper 1 2018-12-19 Iago Toral Quiroga New
[v2,49/53] intel/compiler: fix cmod propagation for non 32-bit types 2018-12-19 Iago Toral Quiroga New
[v2,50/53] intel/compiler: remove MAD/LRP algebraic optimizations from the backend 2018-12-19 Iago Toral Quiroga New
[v2,51/53] intel/compiler: support half-float in the combine constants pass 1 2018-12-19 Iago Toral Quiroga New
[v2,52/53] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 2018-12-19 Iago Toral Quiroga New
[v2,53/53] intel/compiler: allow propagating HF immediates to MAD/LRP 2018-12-19 Iago Toral Quiroga New
anv/device: fix maximum number of images supported 2019-01-11 Iago Toral Quiroga New
anv/pipeline_cache: fix incorrect guards for NIR cache 1 1 2019-01-11 Iago Toral Quiroga Accepted
anv/pipeline_cache: free NIR shader cache 1 1 2019-01-11 Iago Toral Quiroga Accepted
[v2] anv/device: fix maximum number of images supported 2019-01-11 Iago Toral Quiroga New
[v3] anv/device: fix maximum number of images supported 1 2019-01-11 Iago Toral Quiroga New
[v4] anv/device: fix maximum number of images supported 2 2019-01-14 Iago Toral Quiroga New
[v3,01/42] intel/compiler: handle conversions between int and half-float on atom 1 2019-01-15 Iago Toral Quiroga New
[v3,02/42] intel/compiler: add a NIR pass to lower conversions 1 2019-01-15 Iago Toral Quiroga New
[v3,03/42] intel/compiler: split float to 64-bit opcodes from int to 64-bit 2 2019-01-15 Iago Toral Quiroga Accepted
[v3,04/42] intel/compiler: handle b2i/b2f with other integer conversion opcodes 2 2019-01-15 Iago Toral Quiroga Accepted
[v3,05/42] intel/compiler: assert restrictions on conversions to half-float 2 2019-01-15 Iago Toral Quiroga New
[v3,06/42] intel/compiler: lower some 16-bit float operations to 32-bit 2 2019-01-15 Iago Toral Quiroga New
[v3,07/42] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9 1 2019-01-15 Iago Toral Quiroga New
[v3,08/42] intel/compiler: implement 16-bit fsign 2 2019-01-15 Iago Toral Quiroga New
[v3,09/42] intel/compiler: allow extended math functions with HF operands 1 2019-01-15 Iago Toral Quiroga New
[v3,10/42] compiler/nir: add lowering option for 16-bit fmod 1 2019-01-15 Iago Toral Quiroga New
[v3,11/42] intel/compiler: lower 16-bit fmod 1 2019-01-15 Iago Toral Quiroga New
[v3,12/42] compiler/nir: add lowering for 16-bit flrp 1 2019-01-15 Iago Toral Quiroga New
[v3,13/42] intel/compiler: lower 16-bit flrp 1 2019-01-15 Iago Toral Quiroga New
[v3,14/42] compiler/nir: add lowering for 16-bit ldexp 2 2019-01-15 Iago Toral Quiroga New
[v3,15/42] intel/compiler: Extended Math is limited to SIMD8 on half-float 2 2019-01-15 Iago Toral Quiroga New
[v3,16/42] intel/compiler: add instruction setters for Src1Type and Src2Type. 2 2019-01-15 Iago Toral Quiroga New
[v3,17/42] intel/compiler: add new half-float register type for 3-src instructions 1 2019-01-15 Iago Toral Quiroga New
[v3,18/42] intel/compiler: add a helper function to query hardware type table 2019-01-15 Iago Toral Quiroga New
[v3,19/42] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits 2 2019-01-15 Iago Toral Quiroga New
[v3,20/42] intel/compiler: allow half-float on 3-source instructions since gen8 2 2019-01-15 Iago Toral Quiroga New
[v3,21/42] intel/compiler: set correct precision fields for 3-source float instructions 3 2019-01-15 Iago Toral Quiroga New
[v3,22/42] intel/compiler: don't propagate HF immediates to 3-src instructions 2 2019-01-15 Iago Toral Quiroga New
[v3,23/42] intel/compiler: fix ddx and ddy for 16-bit float 2 2019-01-15 Iago Toral Quiroga New
[v3,24/42] intel/compiler: fix ddy for half-float in gen8 2 2019-01-15 Iago Toral Quiroga New
[v3,25/42] intel/compiler: workaround for SIMD8 half-float MAD in gen8 1 2019-01-15 Iago Toral Quiroga New
[v3,26/42] intel/compiler: split is_partial_write() into two variants 2019-01-15 Iago Toral Quiroga New
[v3,27/42] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit 1 2019-01-15 Iago Toral Quiroga New
[v3,28/42] intel/compiler: handle 64-bit float to 8-bit integer conversions 2019-01-15 Iago Toral Quiroga New
[v3,29/42] intel/compiler: handle conversions between int and half-float on atom 1 2019-01-15 Iago Toral Quiroga New
[v3,30/42] intel/compiler: implement isign for int8 1 2019-01-15 Iago Toral Quiroga New
[v3,31/42] intel/compiler: ask for an integer type if requesting an 8-bit type 1 2019-01-15 Iago Toral Quiroga New
[v3,32/42] intel/eu: force stride of 2 on NULL register for Byte instructions 1 2019-01-15 Iago Toral Quiroga New
[v3,33/42] compiler/spirv: add support for Float16 and Int8 capabilities 1 2019-01-15 Iago Toral Quiroga New
[v3,34/42] anv/pipeline: support Float16 and Int8 capabilities in gen8+ 1 2019-01-15 Iago Toral Quiroga New
[v3,35/42] anv/device: expose shaderFloat16 and shaderInt8 in gen8+ 1 2019-01-15 Iago Toral Quiroga New
[v3,36/42] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit 1 2019-01-15 Iago Toral Quiroga New
[v3,37/42] intel/compiler: add a brw_reg_type_is_integer helper 1 2019-01-15 Iago Toral Quiroga New
[v3,38/42] intel/compiler: fix cmod propagation for non 32-bit types 1 2019-01-15 Iago Toral Quiroga New
[v3,39/42] intel/compiler: remove MAD/LRP algebraic optimizations from the backend 1 2019-01-15 Iago Toral Quiroga New
[v3,40/42] intel/compiler: support half-float in the combine constants pass 1 2019-01-15 Iago Toral Quiroga New
[v3,41/42] intel/compiler: fix combine constants for Align16 with half-float prior to gen9 2019-01-15 Iago Toral Quiroga New
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