Patches

Show patches with: Submitter = Paulo Zanoni       |    State = Action Required       |    Archived = No   
« 1 2 3 4 »
Patch A F R T Date Submitter Delegate State
[3/3] drm/i915: fully convert the IRQ initialization macros to intel_uncore 1 2019-04-09 Paulo Zanoni New
[2/3] drm/i915: convert the IRQ initialization functions to intel_uncore 2019-04-09 Paulo Zanoni New
[1/3] drm/i915: refactor the IRQ init/reset macros 1 2019-04-09 Paulo Zanoni New
[CI] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ 1 2018-11-14 Paulo Zanoni New
[CI,3/3] drm/i915: add ICP support to cnp_rawclk() and kill icp_rawclk() 1 2018-11-12 Paulo Zanoni New
[CI,2/3] drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DEN 1 2018-11-12 Paulo Zanoni New
[CI,1/3] drm/i915/cnp+: update to the new RAWCLK_FREQ recommendations 1 2018-11-12 Paulo Zanoni New
[3/3] drm/i915: add ICP support to cnp_rawclk() and kill icp_rawclk() 1 2018-11-10 Paulo Zanoni New
drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ 1 2018-11-09 Paulo Zanoni New
[11/11] drm/i915: pass dev_priv instead of cstate to skl_compute_transition_wm() 1 2018-10-16 Paulo Zanoni New
[10/11] drm/i915: add pipe_htotal to struct skl_wm_params 1 2018-10-16 Paulo Zanoni New
[09/11] drm/i915: make skl_needs_memory_bw_wa() take dev_priv instead of state 1 2018-10-16 Paulo Zanoni New
[08/11] drm/i915: reorganize the error message for invalid watermarks 1 2018-10-16 Paulo Zanoni New
[07/11] drm/i915: move ddb_blocks to be a watermark parameter 1 2018-10-16 Paulo Zanoni New
[06/11] drm/i915: refactor skl_write_plane_wm() 1 2018-10-16 Paulo Zanoni New
[05/11] drm/i915: simplify wm->is_planar assignment 1 2018-10-16 Paulo Zanoni New
[04/11] drm/i915: remove useless memset() for watermarks parameters 1 2018-10-16 Paulo Zanoni New
[03/11] drm/i915: fix handling of invisible planes in watermarks code 1 2018-10-16 Paulo Zanoni New
[01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ 1 2018-10-16 Paulo Zanoni New
drm/i915/cnp+: update to the new RAWCLK_FREQ recommendations 2018-10-12 Paulo Zanoni New
drm/i915/icl: enable SAGV for ICL platform 2 1 2018-10-11 Paulo Zanoni New
[1/6] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+ 2018-10-04 Paulo Zanoni New
[3/3] drm/i915: remove a copy of skl_plane_format_mod_supported() 1 2018-09-25 Paulo Zanoni New
[2/3] drm/i915: make the primary plane func structs const 2018-09-25 Paulo Zanoni New
[5/5] drm/i915: use the SW-based pw->hw_enabled check instead of reading registers 2018-08-20 Paulo Zanoni New
[4/5] drm/i915: move lookup_power_well() up 1 2018-08-20 Paulo Zanoni New
[1/5] drm/i915: kill intel_display_power_well_is_enabled() 2018-08-20 Paulo Zanoni New
[CI,2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL 1 2018-08-17 Paulo Zanoni New
[RFC/CI] drm/i915/icl: account for context save/restore removed bits 2018-08-09 Paulo Zanoni New
[4/4] drm/i915: move lookup_power_well() up 2018-08-08 Paulo Zanoni New
[3/4] drm/i915: use for_each_power_well in lookup_power_well() 1 2018-08-08 Paulo Zanoni New
[2/4] drm/i915: BUG() if we can't lookup_power_well() 2018-08-08 Paulo Zanoni New
[1/4] drm/i915: kill intel_display_power_well_is_enabled() 2018-08-08 Paulo Zanoni New
drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows 2018-07-31 Paulo Zanoni New
[1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider val... 2 2018-07-27 Paulo Zanoni New
[v4,1/5] drm/i915/icl: implement icl_digital_port_connected() 1 2018-07-25 Paulo Zanoni New
drm/i915/icl: implement icl_digital_port_connected() 1 2018-07-25 Paulo Zanoni New
[8/8] drm/i915/icl: toggle PHY clock gating around link training 1 2018-07-11 Paulo Zanoni New
[7/8] drm/i915/icl: program MG_DP_MODE 1 2018-07-11 Paulo Zanoni New
[6/8] drm/i915/icl: Update FIA supported lane count for hpd. 1 2018-07-11 Paulo Zanoni New
[5/8] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI 1 2018-07-11 Paulo Zanoni New
[4/8] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP 1 2018-07-11 Paulo Zanoni New
[3/8] drm/i915/icl: store the port type for TC ports 1 2018-07-11 Paulo Zanoni New
[2/8] drm/i915/icl: implement icl_digital_port_connected() 1 2018-07-11 Paulo Zanoni New
[1/8] drm/i915/icl: compute the TBT PLL registers 2 2018-07-11 Paulo Zanoni New
[CI,2/3] drm/i915/icl: Support for TC North Display interrupts 1 2018-06-16 Paulo Zanoni New
[CI,1/3] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC 1 2018-06-16 Paulo Zanoni New
[CI,2/2] drm/i915/icl: update VBT's child_device_config flags2 field 2 2018-06-14 Paulo Zanoni New
[CI,1/2] drm/i915/icl: implement DVFS for ICL 1 2018-06-14 Paulo Zanoni New
[1/3] drm/i915/i915_reg.h: fix the checkpatch SPACING issues 1 2018-06-12 Paulo Zanoni New
[CI,1/2] drm/i915/icl: fix gmbus gpio pin mapping 1 2018-06-12 Paulo Zanoni New
[CI,2/2] drm/i915/dp: Add support for HBR3 and TPS4 during link training 1 2018-06-11 Paulo Zanoni New
[CI,1/2] drm/i915/icl: Add allowed DP rates for Icelake 1 2018-06-11 Paulo Zanoni New
drm/i915: inline skl_copy_ddb_for_pipe() to its only caller 1 2018-06-07 Paulo Zanoni New
[29/24] drm/i915/icl: DP_AUX_E is valid on ICL+ 1 2018-05-24 Paulo Zanoni New
[27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training 1 2018-05-24 Paulo Zanoni New
[26/24] drm/i915/icl: Add allowed DP rates for Icelake 2 2018-05-24 Paulo Zanoni New
[24/24] drm/i915/icl: toggle PHY clock gating around link training 1 2018-05-22 Paulo Zanoni New
[23/24] drm/i915/icl: program MG_DP_MODE 1 2018-05-22 Paulo Zanoni New
[22/24] drm/i915/icl: Update FIA supported lane count for hpd. 1 2018-05-22 Paulo Zanoni New
[21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI 1 2018-05-22 Paulo Zanoni New
[20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP 2018-05-22 Paulo Zanoni New
[19/24] drm/i915/icl: store the port type for TC ports 2018-05-22 Paulo Zanoni New
[18/24] drm/i915/icl: implement icl_digital_port_connected() 1 2018-05-22 Paulo Zanoni New
[16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT 1 2018-05-22 Paulo Zanoni New
[15/24] drm/i915/icl: compute the TBT PLL registers 2018-05-22 Paulo Zanoni New
[14/24] drm/i915/icl: start adding the TBT pll 1 2018-05-22 Paulo Zanoni New
[12/24] drm/i915/icl: Calculate link clock using the new registers 1 2018-05-22 Paulo Zanoni New
[11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs. 1 2018-05-22 Paulo Zanoni New
[06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE 1 2018-05-22 Paulo Zanoni New
[05/24] drm/i915/icp: Add Interrupt Support 2018-05-22 Paulo Zanoni New
[02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC 2018-05-22 Paulo Zanoni New
drm/i915/icl, x86/gpu: implement ICL stolen memory support 1 2018-05-03 Paulo Zanoni New
[CI] drm/i915/icl: Add configuring MOCS in new Icelake engines 1 2018-05-02 Paulo Zanoni New
drm/i915: enable the pipe/transcoder/planes later on HSW+ 2 2018-05-02 Paulo Zanoni New
drm/i915: configure the transcoder clocks before touching pipeconf on HSW+ 2018-04-27 Paulo Zanoni New
[8/8] drm/i915/icl: Fix the DP Max Voltage for ICL 1 2018-03-28 Paulo Zanoni New
[7/8] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI 2018-03-28 Paulo Zanoni New
[3/8] drm/i915/icl: add basic support for the ICL clocks 2018-03-28 Paulo Zanoni New
[2/8] drm/i915/icl: add definitions for the ICL PLL registers 1 2018-03-28 Paulo Zanoni New
[1/8] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL 1 2018-03-28 Paulo Zanoni New
drm/i915: protect macro parameters in SWING_SEL_{UPP, LO}WER 1 2018-03-23 Paulo Zanoni New
[6/7] drm/i915/icl: Added 5k source scaling support for Gen11 platform 1 2018-03-23 Paulo Zanoni New
[5/7] drm/i915/icl: HPD pin for port F 1 2018-03-23 Paulo Zanoni New
[4/7] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer 1 2018-03-23 Paulo Zanoni New
[3/7] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI 1 2018-03-23 Paulo Zanoni New
[2/7] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake. 1 2018-03-23 Paulo Zanoni New
[08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI 1 2018-03-23 Paulo Zanoni New
[02/17] drm/i915/icl: add basic support for the ICL clocks 2018-03-23 Paulo Zanoni New
[16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes 2018-02-22 Paulo Zanoni New
[15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL 2018-02-22 Paulo Zanoni New
[11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI 2018-02-22 Paulo Zanoni New
[08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI 2 2018-02-22 Paulo Zanoni New
[06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences. 1 2018-02-22 Paulo Zanoni New
[05/17] drm/i915/icl: compute the MG PLL registers 2018-02-22 Paulo Zanoni New
[04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers 1 2018-02-22 Paulo Zanoni New
[03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers 1 2018-02-22 Paulo Zanoni New
[02/17] drm/i915/icl: add basic support for the ICL clocks 1 2018-02-22 Paulo Zanoni New
[01/17] drm/i915/icl: add definitions for the ICL PLL registers 2018-02-22 Paulo Zanoni New
[6/6] drm/i915/icl: program mbus during pipe enable 2 2018-02-05 Paulo Zanoni New
« 1 2 3 4 »