[Mesa-dev,37/95] i965/vec4: use the new helper function to create double immediates

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-38-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
From: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 8a45fde..461e50d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -396,7 +396,7 @@  vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
 
       reg.writemask = writemask;
       if (instr->def.bit_size == 64) {
-         emit(MOV(reg, brw_imm_df(instr->value.f64[i])));
+         emit(MOV(reg, setup_imm_df(instr->value.f64[i])));
       } else {
          emit(MOV(reg, brw_imm_d(instr->value.i32[i])));
       }
@@ -1542,7 +1542,7 @@  vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
    case nir_op_d2b: {
       /* two-argument instructions can't take 64-bit immediates */
       dst_reg zero = dst_reg(this, glsl_type::dvec4_type);
-      emit(MOV(zero, brw_imm_df(0.0)));
+      emit(MOV(zero, setup_imm_df(0.0)));
 
       dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
       emit(CMP(tmp, op[0], src_reg(zero), BRW_CONDITIONAL_NZ));
@@ -1761,7 +1761,7 @@  vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
           */
 
          /* Check for zero */
-         emit(CMP(dst_null_df(), op[0], brw_imm_df(0.0), BRW_CONDITIONAL_NZ));
+         emit(CMP(dst_null_df(), op[0], setup_imm_df(0.0), BRW_CONDITIONAL_NZ));
 
          /* AND each high 32-bit channel with 0x80000000u */
          dst_reg tmp = dst_reg(this, glsl_type::uvec4_type);