[Mesa-dev,50/95] i965/vec4: Use force_vstride0 to fix DF Z/W writes from X/Y channels

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-51-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
A source region like <2,2,1>.xyxy:DF selects XXZZ of a dvec4. If we
have code such as:

mov g2.z g4.x

This creates a problem because we end up writing g4.z in g2.z. To fix
this we want to generate a XXXX region and we can do that by exploiting
again the vstride=0 behavior of the hardware in gen7.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index ea1e530..fd0cafd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2211,6 +2211,13 @@  vec4_visitor::expand_64bit_swizzle_to_32bit()
                inst->src[arg].reg_offset += 1;
             }
             swizzle -= 2;
+         } else {
+            if ((inst->dst.writemask & WRITEMASK_ZW) &&
+                (inst->src[arg].swizzle == BRW_SWIZZLE_XXXX ||
+                 inst->src[arg].swizzle == BRW_SWIZZLE_YYYY) &&
+                 inst->src[arg].file == VGRF) {
+               inst->src[arg].force_vstride0 = true;
+            }
          }
          inst->src[arg].swizzle = BRW_SWIZZLE4(swizzle * 2, swizzle * 2 + 1,
                                                swizzle * 2, swizzle * 2 + 1);