[Mesa-dev,32/95] i965/vec4: implement d2i, d2u, i2d and u2d

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-33-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 81389a9..1525a3d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1116,6 +1116,20 @@  vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
                             BRW_REGISTER_TYPE_F);
       break;
 
+   case nir_op_d2i:
+   case nir_op_d2u:
+      emit_double_to_single(dst, op[0], instr->dest.saturate,
+                            instr->op == nir_op_d2i ? BRW_REGISTER_TYPE_D :
+                                                      BRW_REGISTER_TYPE_UD);
+      break;
+
+   case nir_op_i2d:
+   case nir_op_u2d:
+      emit_single_to_double(dst, op[0], instr->dest.saturate,
+                            instr->op == nir_op_i2d ? BRW_REGISTER_TYPE_D :
+                                                      BRW_REGISTER_TYPE_UD);
+      break;
+
    case nir_op_iadd:
       assert(nir_dest_bit_size(instr->dest.dest) < 64);
    case nir_op_fadd: