[Mesa-dev,20/95] i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW, HIGH}_32BIT

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-21-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
These opcodes do partial writes of 64-bit data. The problem is that we intend
to use them to write on the same register to implement packDouble2x32 and
from the point of view of DCE, since both opcodes write to the same register,
only the last one stands and decides to eliminate the first, which is
not correct, so prevent this from happening.
---
 src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
index 1f7cd49..9056cbf 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
@@ -36,6 +36,12 @@ 
 
 using namespace brw;
 
+static bool
+is_partial_df_write(vec4_instruction *inst) {
+   return inst->opcode == VEC4_OPCODE_SET_LOW_32BIT ||
+          inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT;
+}
+
 bool
 vec4_visitor::dead_code_eliminate()
 {
@@ -115,7 +121,8 @@  vec4_visitor::dead_code_eliminate()
             }
          }
 
-         if (inst->dst.file == VGRF && !inst->predicate) {
+         if (inst->dst.file == VGRF && !inst->predicate &&
+             !is_partial_df_write(inst)) {
             const unsigned offs = type_sz(inst->dst.type) == 8 ?
                1 : (inst->exec_size == 4 ? 0 : 4);
             for (unsigned i = 0; i < inst->regs_written; i++) {