[Mesa-dev,38/95] i965/vec4: allow the vec4 IR to indicate the execution size of instructions

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

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Message ID 1468924892-6910-39-git-send-email-itoral@igalia.com
State New
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Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
In the vec4 backend the generator sets the execution size for all
instructions to 8, however, we will have to split certain DF instructions
to have an execution size of 4, so we need to indicate this explicitly in the
IR for the generator to set the right execution size for them.

We will use this in a later patch when we implement a SIMD splitting pass.
---
 src/mesa/drivers/dri/i965/brw_ir_vec4.h          | 2 ++
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 +++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 1 +
 3 files changed, 6 insertions(+)

Patch hide | download patch | download mbox

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 81b6a13..721772e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -166,6 +166,8 @@  public:
    bool sol_final_write; /**< gen6: send commit message */
    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 
+   uint8_t exec_size;
+
    bool is_send_from_grf();
    unsigned regs_read(unsigned arg) const;
    bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index d7e6e2d..c6e040e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1526,6 +1526,9 @@  generate_code(struct brw_codegen *p,
          }
          brw_set_default_exec_size(p, BRW_EXECUTE_4);
          fix_exec_size = true;
+      } else {
+         assert(inst->exec_size == 8 || inst->exec_size == 4);
+         brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
       }
 
       switch (inst->opcode) {
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 652b453..265bb17 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -55,6 +55,7 @@  vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
    this->mlen = 0;
    this->base_mrf = 0;
    this->offset = 0;
+   this->exec_size = 8;
    this->annotation = NULL;
 }
 

Comments

Iago Toral Quiroga <itoral@igalia.com> writes:

> In the vec4 backend the generator sets the execution size for all
> instructions to 8, however, we will have to split certain DF instructions
> to have an execution size of 4, so we need to indicate this explicitly in the
> IR for the generator to set the right execution size for them.
>
> We will use this in a later patch when we implement a SIMD splitting pass.
> ---
>  src/mesa/drivers/dri/i965/brw_ir_vec4.h          | 2 ++
>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 3 +++
>  src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 1 +
>  3 files changed, 6 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> index 81b6a13..721772e 100644
> --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> @@ -166,6 +166,8 @@ public:
>     bool sol_final_write; /**< gen6: send commit message */
>     unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
>  
> +   uint8_t exec_size;
> +

How about we move this up into backend_instruction instead?  It has the
same semantics as the FS back-end's so it would make sense to share it.

>     bool is_send_from_grf();
>     unsigned regs_read(unsigned arg) const;
>     bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index d7e6e2d..c6e040e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1526,6 +1526,9 @@ generate_code(struct brw_codegen *p,
>           }
>           brw_set_default_exec_size(p, BRW_EXECUTE_4);
>           fix_exec_size = true;

Ugh, the above seems like a nasty hack (which seems to have caused
trouble with double-precision you had to work around in PATCH 14) to
sidestep the missing support for arbitrary execution sizes in the vec4
back-end.  I'd rather drop the hack above and set
vec4_instruction::exec_size to the right size from the visitor when
an execution size other than the default is intended.

> +      } else {
> +         assert(inst->exec_size == 8 || inst->exec_size == 4);

Execution sizes other than these can be valid and potentially useful, I
think I'd drop this assertion.

> +         brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
>        }
>  
>        switch (inst->opcode) {
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 652b453..265bb17 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -55,6 +55,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
>     this->mlen = 0;
>     this->base_mrf = 0;
>     this->offset = 0;
> +   this->exec_size = 8;
>     this->annotation = NULL;
>  }
>  
> -- 
> 2.7.4
>
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