[Mesa-dev,31/95] i965/vec4: implement hardware workaround for align16 double to float conversion

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-32-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
From the BDW PRM, Workarounds chapter:

   "DF->f format conversion for Align16 has wrong emask calculation when
    source is immediate."

So detect the case and move the immediate source to a VGRF before we attempt
the conversion.

Notice that Broadwell and later are strictly scalar at the moment though, so
this is not really necessary.
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 11 +++++++++++
 1 file changed, 11 insertions(+)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 15c829c..81389a9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1027,6 +1027,17 @@  void
 vec4_visitor::emit_double_to_single(dst_reg dst, src_reg src, bool saturate,
                                     brw_reg_type single_type)
 {
+   /* BDW PRM vol 15 - workarounds:
+    * DF->f format conversion for Align16 has wrong emask calculation when
+    * source is immediate.
+    */
+   if (devinfo->gen == 8 && single_type == BRW_REGISTER_TYPE_F &&
+       src.file == BRW_IMMEDIATE_VALUE) {
+      dst_reg fixed_src = dst_reg(this, glsl_type::dvec4_type);
+      emit(MOV(fixed_src, src));
+      src = src_reg(fixed_src);
+   }
+
    dst_reg temp = dst_reg(this, glsl_type::dvec4_type);
    emit(MOV(temp, src));