[Mesa-dev,07/95] i965/vec4/nir: set the right type for 64-bit registers

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-8-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

Not browsing as part of any series.

Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
From: Connor Abbott <connor.w.abbott@intel.com>

---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 +++
 1 file changed, 3 insertions(+)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index df927e7..095a27d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -145,6 +145,9 @@  vec4_visitor::nir_emit_impl(nir_function_impl *impl)
          array_elems *= 2;
 
       nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(array_elems));
+
+      if (reg->bit_size == 64)
+         nir_locals[reg->index].type = BRW_REGISTER_TYPE_DF;
    }
 
    nir_ssa_values = ralloc_array(mem_ctx, dst_reg, impl->ssa_alloc);