[Mesa-dev,26/95] i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-27-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index fde7b60..7b8e30d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -275,15 +275,22 @@  dst_reg_for_nir_reg(vec4_visitor *v, nir_register *nir_reg,
 dst_reg
 vec4_visitor::get_nir_dest(const nir_dest &dest)
 {
+   dst_reg dst;
    if (dest.is_ssa) {
-      dst_reg dst = dst_reg(VGRF, alloc.allocate(dest.ssa.bit_size / 32));
+      dst = dst_reg(VGRF, alloc.allocate(dest.ssa.bit_size / 32));
+      if (dest.ssa.bit_size == 64)
+         dst.type = BRW_REGISTER_TYPE_DF;
       nir_ssa_values[dest.ssa.index] = dst;
       return dst;
    } else {
       unsigned base_offset = dest.reg.base_offset * dest.reg.reg->bit_size / 32;
-      return dst_reg_for_nir_reg(this, dest.reg.reg, base_offset,
-                                 dest.reg.indirect);
+      dst = dst_reg_for_nir_reg(this, dest.reg.reg, base_offset,
+                                dest.reg.indirect);
+      if (dest.reg.reg->bit_size == 64)
+         dst.type = BRW_REGISTER_TYPE_DF;
    }
+
+   return dst;
 }
 
 dst_reg