[Mesa-dev,28/95] i965/vec4: fix register allocation for 64-bit undef sources

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-29-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 7b8e30d..65fa057 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -2009,7 +2009,8 @@  vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
 void
 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
 {
-   nir_ssa_values[instr->def.index] = dst_reg(VGRF, alloc.allocate(1));
+   nir_ssa_values[instr->def.index] =
+      dst_reg(VGRF, alloc.allocate(instr->def.bit_size / 32));
 }
 
 }

Comments

Iago Toral Quiroga <itoral@igalia.com> writes:

> ---
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 7b8e30d..65fa057 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -2009,7 +2009,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
>  void
>  vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
>  {
> -   nir_ssa_values[instr->def.index] = dst_reg(VGRF, alloc.allocate(1));
> +   nir_ssa_values[instr->def.index] =
> +      dst_reg(VGRF, alloc.allocate(instr->def.bit_size / 32));

I think you want to use DIV_ROUND_UP here instead, with that fixed:

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

>  }
>  
>  }
> -- 
> 2.7.4
>
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