[Mesa-dev,03/95] i965/vec4/nir: allocate two registers for dvec3/dvec4

Submitted by Iago Toral Quiroga on July 19, 2016, 10:40 a.m.

Details

Message ID 1468924892-6910-4-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:40 a.m.
From: Connor Abbott <connor.w.abbott@intel.com>

---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 6662a1e..1f8fa80 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -141,6 +141,9 @@  vec4_visitor::nir_emit_impl(nir_function_impl *impl)
       unsigned array_elems =
          reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
 
+      if (reg->bit_size == 64)
+         array_elems *= 2;
+
       nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(array_elems));
    }
 
@@ -270,7 +273,7 @@  dst_reg
 vec4_visitor::get_nir_dest(const nir_dest &dest)
 {
    if (dest.is_ssa) {
-      dst_reg dst = dst_reg(VGRF, alloc.allocate(1));
+      dst_reg dst = dst_reg(VGRF, alloc.allocate(dest.ssa.bit_size / 32));
       nir_ssa_values[dest.ssa.index] = dst;
       return dst;
    } else {

Comments

Iago Toral Quiroga <itoral@igalia.com> writes:

> From: Connor Abbott <connor.w.abbott@intel.com>
>
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 6662a1e..1f8fa80 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -141,6 +141,9 @@ vec4_visitor::nir_emit_impl(nir_function_impl *impl)
>        unsigned array_elems =
>           reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
>  
> +      if (reg->bit_size == 64)
> +         array_elems *= 2;
> +
>        nir_locals[reg->index] = dst_reg(VGRF, alloc.allocate(array_elems));

Shouldn't this just be 'array_elems * DIV_ROUND_UP(bit_size, 32)'?
Seems like a saner long-term plan than special-casing every possible bit
size in every place that cares about the bit size of a variable.

>     }
>  
> @@ -270,7 +273,7 @@ dst_reg
>  vec4_visitor::get_nir_dest(const nir_dest &dest)
>  {
>     if (dest.is_ssa) {
> -      dst_reg dst = dst_reg(VGRF, alloc.allocate(1));
> +      dst_reg dst = dst_reg(VGRF, alloc.allocate(dest.ssa.bit_size / 32));

Using DIV_ROUND_UP instead of plain integer division would have the
advantage that it won't leave things so badly broken for sub-32-bit
types.

>        nir_ssa_values[dest.ssa.index] = dst;
>        return dst;
>     } else {
> -- 
> 2.7.4
>
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