[Mesa-dev,68/95] i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions

Submitted by Iago Toral Quiroga on July 19, 2016, 10:41 a.m.

Details

Message ID 1468924892-6910-69-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:41 a.m.
In gen < 8 instructions that write more than one register need to read
more than one register too. Make sure we don't break that restriction
by copy propagating from a uniform.
---
 src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index 6f52eec..d284528 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -322,6 +322,13 @@  try_copy_propagate(const struct brw_device_info *devinfo,
        value.file != ATTR)
       return false;
 
+   /* In gen < 8 instructions that write 2 registers also need to read 2
+    * registers. Make sure we don't break that restriction by copy
+    * propagating from a uniform.
+    */
+   if (devinfo->gen < 8 && inst->regs_written > 1 && is_uniform(value))
+      return false;
+
    /* If the type of the copy value is different from the type of the
     * instruction then the swizzles and writemasks involved don't have the same
     * meaning and simply replacing the source would produce different semantics.