[Mesa-dev,74/95] i965/vec4: do not split scratch read/write opcodes

Submitted by Iago Toral Quiroga on July 19, 2016, 10:41 a.m.

Details

Message ID 1468924892-6910-75-git-send-email-itoral@igalia.com
State New
Headers show
Series "i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0" ( rev: 2 1 ) in Mesa

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Commit Message

Iago Toral Quiroga July 19, 2016, 10:41 a.m.
64-bit scratch read/writes require to shuffle data around so we need
to have access to the full 64-bit data. We will do the right thing
for these when we emit the messages.
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

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diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 9672b2c..99b30ce 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2036,6 +2036,15 @@  get_lowered_simd_width(const struct brw_device_info *devinfo,
    if (devinfo->gen != 7 || inst->regs_written < 2)
       return inst->exec_size;
 
+   /* Do not split some instructions that require special handling */
+   switch (inst->opcode) {
+   case SHADER_OPCODE_GEN4_SCRATCH_READ:
+   case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+      return inst->exec_size;
+   default:
+      break;
+   }
+
    unsigned lowered_width = MIN2(8, inst->exec_size);
 
    /* Align16 8-wide double-precision bcsel does not work well. Verified