[Mesa-dev,2/4] i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.

Submitted by Francisco Jerez on July 1, 2016, 5:07 a.m.

Details

Message ID 20160701050744.26228-2-currojerez@riseup.net
State New
Headers show
Series "i965: adds gen7_emit_cs_stall_flush on intel_texture_barrier" ( rev: 5 ) in Mesa

Not browsing as part of any series.

Commit Message

Francisco Jerez July 1, 2016, 5:07 a.m.
There were two places in the driver doing a pipe control VF cache
flush, one of them was missing this workaround, move it down into
brw_emit_pipe_control_flush to make sure we don't miss it again.
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 586355d..14a8f7c 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -100,6 +100,16 @@  brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
       if (brw->gen == 8)
          gen8_add_cs_stall_workaround_bits(&flags);
 
+      if (brw->gen == 9 &&
+          (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
+         /* Hardware workaround: SKL
+          *
+          * Emit Pipe Control with all bits set to zero before emitting
+          * a Pipe Control with VF Cache Invalidate set.
+          */
+         brw_emit_pipe_control_flush(brw, 0);
+      }
+
       BEGIN_BATCH(6);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
       OUT_BATCH(flags);
@@ -322,15 +332,6 @@  brw_emit_mi_flush(struct brw_context *brw)
    } else {
       int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
       if (brw->gen >= 6) {
-         if (brw->gen == 9) {
-            /* Hardware workaround: SKL
-             *
-             * Emit Pipe Control with all bits set to zero before emitting
-             * a Pipe Control with VF Cache Invalidate set.
-             */
-            brw_emit_pipe_control_flush(brw, 0);
-         }
-
          flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                   PIPE_CONTROL_VF_CACHE_INVALIDATE |

Comments

Looks good to me:

Reviewed-by: Alejandro PiƱeiro <apinheiro@igalia.com>

Note: I think that patches 3-4 should be reviewed by a more seasoned
developer (specially patch 3).

On 01/07/16 07:07, Francisco Jerez wrote:
> There were two places in the driver doing a pipe control VF cache
> flush, one of them was missing this workaround, move it down into
> brw_emit_pipe_control_flush to make sure we don't miss it again.
> ---
>  src/mesa/drivers/dri/i965/brw_pipe_control.c | 19 ++++++++++---------
>  1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> index 586355d..14a8f7c 100644
> --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
> +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
> @@ -100,6 +100,16 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
>        if (brw->gen == 8)
>           gen8_add_cs_stall_workaround_bits(&flags);
>  
> +      if (brw->gen == 9 &&
> +          (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
> +         /* Hardware workaround: SKL
> +          *
> +          * Emit Pipe Control with all bits set to zero before emitting
> +          * a Pipe Control with VF Cache Invalidate set.
> +          */
> +         brw_emit_pipe_control_flush(brw, 0);
> +      }
> +
>        BEGIN_BATCH(6);
>        OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
>        OUT_BATCH(flags);
> @@ -322,15 +332,6 @@ brw_emit_mi_flush(struct brw_context *brw)
>     } else {
>        int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
>        if (brw->gen >= 6) {
> -         if (brw->gen == 9) {
> -            /* Hardware workaround: SKL
> -             *
> -             * Emit Pipe Control with all bits set to zero before emitting
> -             * a Pipe Control with VF Cache Invalidate set.
> -             */
> -            brw_emit_pipe_control_flush(brw, 0);
> -         }
> -
>           flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
>                    PIPE_CONTROL_DEPTH_CACHE_FLUSH |
>                    PIPE_CONTROL_VF_CACHE_INVALIDATE |