rnndb: mdp5: Remove MDP offsets

Submitted by Archit Taneja on June 27, 2016, 6:52 a.m.

Details

Message ID 1467010362-19612-1-git-send-email-architt@codeaurora.org
State New
Headers show
Series "rnndb: mdp5: Remove MDP offsets" ( rev: 1 ) in DRI devel

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Commit Message

Archit Taneja June 27, 2016, 6:52 a.m.
MDSS and MDP5 have been separated out in the kernel driver. We no
longer need to keep a track of the start of MDP addesses within
MDSS.

Also, clean up the MDP5 register name prefix. Change it from
"REG_MDP5_MDP_" to "REG_MDP5_".

Signed-off-by: Archit Taneja <architt@codeaurora.org>
---
Used by the "Enable DT Support" kernel patchset:

https://lists.freedesktop.org/archives/dri-devel/2016-June/111837.html


 rnndb/mdp/mdp5.xml | 127 ++++++++++++++++++++++++++---------------------------
 1 file changed, 62 insertions(+), 65 deletions(-)

Patch hide | download patch | download mbox

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index c829737..de9560b 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -139,74 +139,71 @@  xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 		<bitfield name="CLIENT2" low="16" high="23" type="uint"/>
 	</bitset>
 
-	<!-- Even though there is 1 MDP, length=2 to force dynamic offset usage -->
-	<array doffsets="mdp5_cfg->mdp.base[0]" name="MDP" length="2" stride="0x1000">
-		<reg32 offset="0x00000" name="HW_VERSION">
-			<bitfield name="STEP" low="0" high="15" type="uint"/>
-			<bitfield name="MINOR" low="16" high="27" type="uint"/>
-			<bitfield name="MAJOR" low="28" high="31" type="uint"/>
-		</reg32>
-
-		<reg32 offset="0x00004" name="DISP_INTF_SEL">
-			<bitfield name="INTF0" low="0"  high="7"  type="mdp5_intf_type"/>
-			<bitfield name="INTF1" low="8"  high="15" type="mdp5_intf_type"/>
-			<bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
-			<bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
-		</reg32>
-		<reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
-		<reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
-		<reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
-		<reg32 offset="0x0001C" name="HIST_INTR_EN"/>
-		<reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
-		<reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
-		<reg32 offset="0x00028" name="SPARE_0">
-			<bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
-		</reg32>
-
-		<array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
-			<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
-		</array>
-		<array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
-			<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
-		</array>
+	<reg32 offset="0x00000" name="HW_VERSION">
+		<bitfield name="STEP" low="0" high="15" type="uint"/>
+		<bitfield name="MINOR" low="16" high="27" type="uint"/>
+		<bitfield name="MAJOR" low="28" high="31" type="uint"/>
+	</reg32>
+
+	<reg32 offset="0x00004" name="DISP_INTF_SEL">
+		<bitfield name="INTF0" low="0"  high="7"  type="mdp5_intf_type"/>
+		<bitfield name="INTF1" low="8"  high="15" type="mdp5_intf_type"/>
+		<bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
+		<bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
+	</reg32>
+	<reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
+	<reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
+	<reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
+	<reg32 offset="0x0001C" name="HIST_INTR_EN"/>
+	<reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
+	<reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
+	<reg32 offset="0x00028" name="SPARE_0">
+		<bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
+	</reg32>
 
-		<enum name="mdp5_igc_type">
-			<value name="IGC_VIG" value="0"/>		<!-- 0x200 -->
-			<value name="IGC_RGB" value="1"/>		<!-- 0x210 -->
-			<value name="IGC_DMA" value="2"/>		<!-- 0x220 -->
-			<value name="IGC_DSPP" value="3"/>		<!-- 0x300 -->
-		</enum>
-		<array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
-			<array offset="0x00" name="LUT" length="3" stride="4">
-				<reg32 offset="0" name="REG">
-					<bitfield name="VAL" low="0" high="11"/>
-					<bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
-					<!--
-						not sure about these:
-							/* INDEX_UPDATE */
-							data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
-							MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
-					-->
-					<bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
-					<bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
-					<bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
-				</reg32>
-			</array>
+	<array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
+		<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
+	</array>
+	<array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
+		<reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
+	</array>
+
+	<enum name="mdp5_igc_type">
+		<value name="IGC_VIG" value="0"/>		<!-- 0x200 -->
+		<value name="IGC_RGB" value="1"/>		<!-- 0x210 -->
+		<value name="IGC_DMA" value="2"/>		<!-- 0x220 -->
+		<value name="IGC_DSPP" value="3"/>		<!-- 0x300 -->
+	</enum>
+	<array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
+		<array offset="0x00" name="LUT" length="3" stride="4">
+			<reg32 offset="0" name="REG">
+				<bitfield name="VAL" low="0" high="11"/>
+				<bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
+				<!--
+					not sure about these:
+						/* INDEX_UPDATE */
+						data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
+						MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
+				-->
+				<bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
+				<bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
+				<bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
+			</reg32>
 		</array>
-		<reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
-		<reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
-			<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
-			<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
-			<bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
-			<bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
-		</reg32>
-		<reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
-			<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
-			<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
-			<bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
-			<bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
-		</reg32>
 	</array>
+	<reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
+	<reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
+		<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
+		<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
+		<bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
+		<bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
+	</reg32>
+	<reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
+		<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
+		<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
+		<bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
+		<bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
+	</reg32>
 
 <!-- check length/index.. -->
 	<array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">