[05/12] Backend: Refine return value of sub_group_all/any to 1

Submitted by Pan Xiuli on May 26, 2016, 3:14 a.m.

Details

Message ID 1464232467-16231-5-git-send-email-xiuli.pan@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Beignet

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Commit Message

Pan Xiuli May 26, 2016, 3:14 a.m.
From: Pan Xiuli <xiuli.pan@intel.com>

The old sub_group_all/any will return 65535 as true. Refine them to 1.
V2: Remove unused value.

Signed-off-by: Pan Xiuli <xiuli.pan@intel.com>
---
 backend/src/backend/gen_insn_selection.cpp | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

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diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index fbd9363..09f459a 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2697,12 +2697,13 @@  extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
           case ir::OP_SIMD_ANY:
             {
               const GenRegister constZero = GenRegister::immuw(0);;
-              const GenRegister regOne = GenRegister::uw1grf(ir::ocl::one);
+              const GenRegister constOne = GenRegister::retype(sel.selReg(sel.reg(ir::FAMILY_DWORD)), GEN_TYPE_UD);
               const GenRegister flag01 = GenRegister::flag(0, 1);
 
               sel.push();
                 int simdWidth = sel.curr.execWidth;
                 sel.curr.predicate = GEN_PREDICATE_NONE;
+                sel.MOV(constOne, GenRegister::immud(1));
                 sel.curr.execWidth = 1;
                 sel.curr.noMask = 1;
                 sel.MOV(flag01, constZero);
@@ -2719,19 +2720,21 @@  extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
                   sel.curr.predicate = GEN_PREDICATE_ALIGN1_ANY8H;
                 else
                   NOT_IMPLEMENTED;
-                sel.SEL(dst, regOne, constZero);
+                sel.SEL(dst, constOne, constZero);
               sel.pop();
             }
             break;
           case ir::OP_SIMD_ALL:
             {
               const GenRegister constZero = GenRegister::immuw(0);
+              const GenRegister constOne = GenRegister::retype(sel.selReg(sel.reg(ir::FAMILY_DWORD)), GEN_TYPE_UD);
               const GenRegister regOne = GenRegister::uw1grf(ir::ocl::one);
               const GenRegister flag01 = GenRegister::flag(0, 1);
 
               sel.push();
                 int simdWidth = sel.curr.execWidth;
                 sel.curr.predicate = GEN_PREDICATE_NONE;
+                sel.MOV(constOne, GenRegister::immud(1));
                 sel.curr.execWidth = 1;
                 sel.curr.noMask = 1;
                 sel.MOV(flag01, regOne);
@@ -2749,7 +2752,7 @@  extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
                   sel.curr.predicate = GEN_PREDICATE_ALIGN1_ALL8H;
                 else
                   NOT_IMPLEMENTED;
-                sel.SEL(dst, regOne, constZero);
+                sel.SEL(dst, constOne, constZero);
               sel.pop();
             }
             break;