[11/21] drm/i915/slpc: Send reset event

Submitted by tom.orourke@intel.com on April 28, 2016, 1:10 a.m.

Details

Message ID 1461805865-212590-12-git-send-email-tom.orourke@intel.com
State New
Headers show
Series "Add support for GuC-based SLPC" ( rev: 4 ) in Intel GFX

Not browsing as part of any series.

Commit Message

tom.orourke@intel.com April 28, 2016, 1:10 a.m.
From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Add host2guc SLPC reset event and send reset event
during enable.

v2: extract host2guc_slpc to handle slpc status code
    coding style changes (Paulo)

Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
---
 drivers/gpu/drm/i915/intel_slpc.c | 33 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++
 2 files changed, 46 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index bacbfed..3fd46ac 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -26,6 +26,36 @@ 
 #include "i915_drv.h"
 #include "intel_guc.h"
 
+static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len)
+{
+	int ret = host2guc_action(&dev_priv->guc, data, len);
+
+	if (!ret) {
+		ret = I915_READ(SOFT_SCRATCH(1));
+		ret &= SLPC_EVENT_STATUS_MASK;
+	}
+
+	if (ret)
+		DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret);
+}
+
+static void host2guc_slpc_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_i915_gem_object *obj = dev_priv->guc.slpc.shared_data_obj;
+	u32 data[4];
+	u64 shared_data_gtt_offset = i915_gem_obj_ggtt_offset(obj);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+	data[2] = lower_32_bits(shared_data_gtt_offset);
+	data[3] = upper_32_bits(shared_data_gtt_offset);
+
+	WARN_ON(data[3] != 0);
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static u8 slpc_get_platform_sku(struct drm_i915_gem_object *obj)
 {
 	struct drm_device *dev = obj->base.dev;
@@ -132,7 +162,8 @@  void intel_slpc_disable(struct drm_device *dev)
 
 void intel_slpc_enable(struct drm_device *dev)
 {
-	return;
+	if (intel_slpc_active(dev))
+		host2guc_slpc_reset(dev);
 }
 
 void intel_slpc_reset(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 9badca9..0a9c0f2 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,20 @@ 
 #define SLPC_MINOR_VER 4
 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER))
 
+enum slpc_event_id {
+	SLPC_EVENT_RESET = 0,
+	SLPC_EVENT_SHUTDOWN = 1,
+	SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+	SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+	SLPC_EVENT_FLIP_COMPLETE = 4,
+	SLPC_EVENT_QUERY_TASK_STATE = 5,
+	SLPC_EVENT_PARAMETER_SET = 6,
+	SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_EVENT_STATUS_MASK	0xFF
+
 enum slpc_global_state {
 	SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
 	SLPC_GLOBAL_STATE_INITIALIZING = 1,