[13/16] drm/i915: Extract raw GPU timestamps from OA reports to forward in perf samples

Submitted by sourab.gupta@intel.com on April 22, 2016, 11:34 a.m.

Details

Message ID 1461324845-25755-14-git-send-email-sourab.gupta@intel.com
State New
Headers show
Series "Framework to collect command stream gpu metrics using i915 perf" ( rev: 1 ) in Intel GFX

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Commit Message

sourab.gupta@intel.com April 22, 2016, 11:34 a.m.
From: Sourab Gupta <sourab.gupta@intel.com>

The OA reports contain the least significant 32 bits of the gpu timestamp.
This patch enables retrieval of the timestamp field from OA reports, to
forward as 64 bit raw gpu timestamps in the perf samples.

Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/i915_perf.c | 44 ++++++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h  |  4 ++++
 3 files changed, 38 insertions(+), 11 deletions(-)

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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bdc7ad4..2ac07fb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2179,6 +2179,7 @@  struct drm_i915_private {
 			u32 ctx_flexeu0_off;
 			u32 n_pending_periodic_samples;
 			u32 pending_periodic_ts;
+			u64 last_gpu_ts;
 
 			struct i915_oa_ops ops;
 			const struct i915_oa_format *oa_formats;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index f1c26e5..2bf9cf0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -775,6 +775,24 @@  static int append_sample(struct i915_perf_stream *stream,
 	return 0;
 }
 
+static u64 get_gpu_ts_from_oa_report(struct drm_i915_private *dev_priv,
+					const u8 *report)
+{
+	u32 sample_ts = *(u32 *)(report + 4);
+	u32 delta;
+
+	/*
+	 * NB: We have to assume we're updating last_gpu_ts frequently
+	 * enough that it's never possible to see multiple overflows before
+	 * we compare sample_ts to last_gpu_ts. Since this is significantly
+	 * large duration (~6min for 80ns ts base), we can safely assume so.
+	 */
+	delta = sample_ts - (u32)dev_priv->perf.oa.last_gpu_ts;
+	dev_priv->perf.oa.last_gpu_ts += delta;
+
+	return dev_priv->perf.oa.last_gpu_ts;
+}
+
 static int append_oa_buffer_sample(struct i915_perf_stream *stream,
 				    struct i915_perf_read_state *read_state,
 				    const u8 *report)
@@ -811,10 +829,9 @@  static int append_oa_buffer_sample(struct i915_perf_stream *stream,
 	if (sample_flags & SAMPLE_TAG)
 		data.tag = dev_priv->perf.last_tag;
 
-	/* Derive timestamp from OA report, after scaling with the ts base */
-#warning "FIXME: append_oa_buffer_sample: derive the timestamp from OA report"
+	/* Derive timestamp from OA report */
 	if (sample_flags & SAMPLE_TS)
-		data.ts = 0;
+		data.ts = get_gpu_ts_from_oa_report(dev_priv, report);
 
 	if (sample_flags & SAMPLE_OA_REPORT)
 		data.report = report;
@@ -1226,6 +1243,7 @@  static int append_one_cs_sample(struct i915_perf_stream *stream,
 	enum intel_engine_id id = stream->engine;
 	struct sample_data data = { 0 };
 	u32 sample_flags = stream->sample_flags;
+	u64 gpu_ts = 0;
 	int ret = 0;
 
 	if (sample_flags & SAMPLE_OA_REPORT) {
@@ -1242,6 +1260,9 @@  static int append_one_cs_sample(struct i915_perf_stream *stream,
 						U32_MAX);
 		if (ret)
 			return ret;
+
+		if (sample_flags & SAMPLE_TS)
+			gpu_ts = get_gpu_ts_from_oa_report(dev_priv, report);
 	}
 
 	if (sample_flags & SAMPLE_OA_SOURCE_INFO)
@@ -1263,17 +1284,14 @@  static int append_one_cs_sample(struct i915_perf_stream *stream,
 	}
 
 	if (sample_flags & SAMPLE_TS) {
-		/* For RCS, if OA samples are also being collected, derive the
-		 * timestamp from OA report, after scaling with the TS base.
+		/* If OA sampling is enabled, derive the ts from OA report.
 		 * Else, forward the timestamp collected via command stream.
 		 */
-#warning "FIXME: append_one_cs_sample: derive the timestamp from OA report"
-		if (sample_flags & SAMPLE_OA_REPORT)
-			data.ts = 0;
-		else
-			data.ts = *(u64 *)
+		if (!(sample_flags & SAMPLE_OA_REPORT))
+			gpu_ts = *(u64 *)
 				(dev_priv->perf.command_stream_buf[id].addr +
 					node->ts_offset);
+		data.ts = gpu_ts;
 	}
 
 	return append_sample(stream, read_state, &data);
@@ -2025,8 +2043,12 @@  static void i915_ring_stream_enable(struct i915_perf_stream *stream)
 {
 	struct drm_i915_private *dev_priv = stream->dev_priv;
 
-	if (stream->sample_flags & SAMPLE_OA_REPORT)
+	if (stream->sample_flags & SAMPLE_OA_REPORT) {
+		dev_priv->perf.oa.last_gpu_ts =
+			((u64)I915_READ(GT_TIMESTAMP_COUNT_UDW) << 32) |
+			I915_READ(GT_TIMESTAMP_COUNT);
 		dev_priv->perf.oa.ops.oa_enable(dev_priv);
+	}
 
 	if (stream->cs_mode)
 		stream->command_stream_hook = i915_ring_stream_cs_hook;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0924e4f..2584c0b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -573,6 +573,10 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
 #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
 
+/* Timestamp count register */
+#define GT_TIMESTAMP_COUNT		_MMIO(0x2358)
+#define GT_TIMESTAMP_COUNT_UDW		_MMIO(0x2358 + 4)
+
 /* There are the 4 64-bit counter registers, one for each stream output */
 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)