[02/14] drm/i915/tdr: Extend the idea of reset_counter to engine reset

Submitted by arun.siluvery@linux.intel.com on April 12, 2016, 4:59 p.m.

Details

Message ID 1460480381-8777-3-git-send-email-arun.siluvery@linux.intel.com
State New
Headers show
Series "Gen8 Execlist based Engine reset and recovery support" ( rev: 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

arun.siluvery@linux.intel.com April 12, 2016, 4:59 p.m.
This change extends the idea of reset_counter variable to engine reset by
creating additional variables for each engine. Least significant bit is set
to mark the engine reset is pending and once reset is successful it is
incremented again, this is further used to count the no of engine resets.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5424016..ca9b1ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1370,6 +1370,12 @@  struct i915_gpu_error {
 #define I915_RESET_IN_PROGRESS_FLAG	1
 #define I915_WEDGED			(1 << 31)
 
+	/* indicates request to reset engine */
+#define I915_ENGINE_RESET_IN_PROGRESS	(1<<0)
+
+	/* extending the idea of reset_counter to engine reset */
+	atomic_t engine_reset_counter[I915_NUM_ENGINES];
+
 	/**
 	 * Waitqueue to signal when the reset has completed. Used by clients
 	 * that wait for dev_priv->mm.wedged to settle.
@@ -3059,6 +3065,19 @@  static inline u32 i915_reset_count(struct i915_gpu_error *error)
 	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
 }
 
+static inline bool i915_engine_reset_in_progress(struct i915_gpu_error *error,
+						 u32 engine_id)
+{
+	return unlikely(atomic_read(&error->engine_reset_counter[engine_id])
+			& I915_ENGINE_RESET_IN_PROGRESS);
+}
+
+static inline u32 i915_engine_reset_count(struct i915_gpu_error *error,
+					  struct intel_engine_cs *engine)
+{
+	return (atomic_read(&error->engine_reset_counter[engine->id]) + 1) / 2;
+}
+
 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
 {
 	return dev_priv->gpu_error.stop_rings == 0 ||