[RFCv3,13/15] drm/i915: Introduce GVT context creation API

Submitted by Wang, Zhi A on March 11, 2016, 10:59 a.m.

Details

Message ID 1457693986-6892-14-git-send-email-zhi.a.wang@intel.com
State New
Headers show
Series "Introduce GVT context support" ( rev: 1 ) in Intel GFX

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Commit Message

Wang, Zhi A March 11, 2016, 10:59 a.m.
GVT workload scheduler needs special host LRC contexts, the so called
"shadow LRC context" to submit guest workload to host i915. During the
guest workload submission, GVT fills the shadow LRC context with the
content of guest LRC context: engine context is copied without changes,
ring context is mostly owned by host i915.

The GVT-g workload scheduler flow:

         +-----------+                   +-----------+
         | GVT Guest |                   | GVT Guest |
         +-+-----^---+                   +-+-----^---+
           |     |                         |     |
           |     | GVT-g                   |     | GVT-g
vELSP write|     | emulates     vELSP write|     | emulates
           |     | Execlist/CSB            |     | Execlist/CSB
           |     | Status                  |     | Status
           |     |                         |     |
    +------v-----+-------------------------v-----+---------+
    |           GVT Virtual Execlist Submission            |
    +------+-------------------------------+---------------+
           |                               |
           | Per-VM/Ring Workoad Q         | Per-VM/Ring Workload Q
   +---------------------+--+      +------------------------+
       +---v--------+    ^             +---v--------+
       |GVT Workload|... |             |GVT Workload|...
       +------------+    |             +------------+
                         |
                         | Pick Workload from Q
    +--------------------+---------------------------------+
    |                GVT Workload Scheduler                |
    +--------------------+---------------------------------+
                         |         * Shadow guest LRC context
                  +------v------+  * Shadow guest ring buffer
                  | GVT Context |  * Scan/Patch guest RB instructions
                  +------+------+
                         |
                         v
              Host i915 GEM Submission

v2:

Mostly based on Daniel's idea. Call the refactored core logic of GEM
context creation service and LRC context creation service to create the GVT
context.

Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 52 +++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d7fc738..26106e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3270,6 +3270,7 @@  i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
 void i915_gem_context_free(struct kref *ctx_ref);
 struct drm_i915_gem_object *
 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
+struct intel_context *i915_gem_create_gvt_context(struct drm_device *dev);
 static inline void i915_gem_context_reference(struct intel_context *ctx)
 {
 	kref_get(&ctx->ref);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index e7415b1a..a9d5f17 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -369,6 +369,58 @@  i915_gem_create_context(struct drm_device *dev,
 	return ctx;
 }
 
+/**
+ * i915_gem_create_gvt_context - create a GVT GEM context
+ * @dev: drm device *
+ *
+ * This function is used to create a GVT specific GEM context.
+ *
+ * Returns:
+ * pointer to intel_context on success, NULL if failed
+ *
+ */
+struct intel_context *
+i915_gem_create_gvt_context(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct i915_gem_context_create_params params;
+	struct intel_lr_context_alloc_params alloc_params;
+	struct intel_context *ctx;
+	int i, ret;
+
+	memset(&params, 0, sizeof(params));
+	memset(&alloc_params, 0, sizeof(alloc_params));
+
+	params.file_priv = NULL;
+	params.has_legacy_ctx = false;
+	params.has_ppgtt = false;
+	params.is_global_default_ctx = false;
+
+	alloc_params.ctx_needs_init = false;
+	alloc_params.ctx_needs_status_change_notification = true;
+	alloc_params.ctx_needs_single_submission = true;
+	alloc_params.ringbuffer_size = 512 * PAGE_SIZE;
+
+	mutex_lock(&dev->struct_mutex);
+
+	ctx = __i915_gem_create_context(dev, &params);
+	if (IS_ERR(ctx))
+		return ctx;
+
+	for (i = 0; i < I915_NUM_RINGS; i++) {
+		alloc_params.ring = &dev_priv->ring[i];
+		ret = __intel_lr_context_deferred_alloc(ctx, &alloc_params);
+		if (ret) {
+			i915_gem_context_unreference(ctx);
+			ctx = NULL;
+			goto out;
+		}
+	}
+out:
+	mutex_unlock(&dev->struct_mutex);
+	return ctx;
+}
+
 static void i915_gem_context_unpin(struct intel_context *ctx,
 				   struct intel_engine_cs *engine)
 {