drm/i915: GPIO for BXT generic MIPI

Submitted by Deepak M on March 11, 2016, 10:51 a.m.

Details

Message ID 1457693476-13242-1-git-send-email-m.deepak@intel.com
State New
Headers show
Series "drm/i915: GPIO for BXT generic MIPI" ( rev: 2 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Deepak M March 11, 2016, 10:51 a.m.
Added the BXT GPIO pin configuration and programming logic for
backlight and panel control.

v2 by Deepak
  - Added the GPIO table for BXT.
  - Added gpio_free

v3 by Deepak
  - requesting the gpio once
  - freeing the gpio while unloading

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---

GPIO mapping table can be found in the below link:
https://drive.google.com/drive/folders/0BxSYm2johowAaE94S0ZvbE1wTG8

 drivers/gpu/drm/i915/intel_dsi.c           |   6 +
 drivers/gpu/drm/i915/intel_dsi.h           |   2 +-
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 687 +++++++++++++++++++++++++++++
 3 files changed, 694 insertions(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b928c50..30994f5 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -39,10 +39,12 @@ 
 static const struct {
 	u16 panel_id;
 	struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
+	void (*exit)(struct intel_dsi *intel_dsi);
 } intel_dsi_drivers[] = {
 	{
 		.panel_id = MIPI_DSI_GENERIC_PANEL_ID,
 		.init = vbt_panel_init,
+		.exit = vbt_panel_exit,
 	},
 };
 
@@ -1073,6 +1075,7 @@  static void intel_dsi_connector_destroy(struct drm_connector *connector)
 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+	int i;
 
 	if (intel_dsi->panel) {
 		drm_panel_detach(intel_dsi->panel);
@@ -1084,6 +1087,9 @@  static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
 	if (intel_dsi->gpio_panel)
 		gpiod_put(intel_dsi->gpio_panel);
 
+	for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++)
+		intel_dsi_drivers[i].exit(intel_dsi);
+
 	intel_encoder_destroy(encoder);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index de7be7f..2f833b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -131,5 +131,5 @@  extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
 							enum port port);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
-
+void vbt_panel_exit(struct intel_dsi *intel_dsi);
 #endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 6b9a1f7..f8b126b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@ 
 #include <drm/drm_edid.h>
 #include <drm/i915_drm.h>
 #include <drm/drm_panel.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <video/mipi_display.h>
 #include <asm/intel-mid.h>
@@ -615,6 +616,635 @@  static struct gpio_table gtable[] = {
 	{ VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0, VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
 };
 
+struct bxt_gpio_table {
+	u16 gpio_pin;
+	u16 offset;
+	bool pin_requested;
+};
+
+#define  BXT_HV_DDI0_DDC_SDA_PIN                187
+#define  BXT_HV_DDI0_DDC_SCL_PIN                188
+#define  BXT_HV_DDI1_DDC_SDA_PIN                189
+#define  BXT_HV_DDI1_DDC_SCL_PIN                190
+#define  BXT_DBI_SDA_PIN                        191
+#define  BXT_DBI_SCL_PIN                        192
+#define  BXT_PANEL0_VDDEN_PIN                   193
+#define  BXT_PANEL0_BKLTEN_PIN                  194
+#define  BXT_PANEL0_BKLTCTL_PIN                 195
+#define  BXT_PANEL1_VDDEN_PIN                   196
+#define  BXT_PANEL1_BKLTEN_PIN                  197
+#define  BXT_PANEL1_BKLTCTL_PIN                 198
+#define  BXT_DBI_CSX_PIN                        199
+#define  BXT_DBI_RESX_PIN                       200
+#define  BXT_GP_INTD_DSI_TE1_PIN                201
+#define  BXT_GP_INTD_DSI_TE2_PIN                202
+#define  BXT_USB_OC0_B_PIN                      203
+#define  BXT_USB_OC1_B_PIN                      204
+#define  BXT_MEX_WAKE0_B_PIN                    205
+#define  BXT_MEX_WAKE1_B_PIN                    206
+#define  BXT_EMMC0_CLK_PIN                      156
+#define  BXT_EMMC0_D0_PIN                       157
+#define  BXT_EMMC0_D1_PIN                       158
+#define  BXT_EMMC0_D2_PIN                       159
+#define  BXT_EMMC0_D3_PIN                       160
+#define  BXT_EMMC0_D4_PIN                       161
+#define  BXT_EMMC0_D5_PIN                       162
+#define  BXT_EMMC0_D6_PIN                       163
+#define  BXT_EMMC0_D7_PIN                       164
+#define  BXT_EMMC0_CMD_PIN                      165
+#define  BXT_SDIO_CLK_PIN                       166
+#define  BXT_SDIO_D0_PIN                        167
+#define  BXT_SDIO_D1_PIN                        168
+#define  BXT_SDIO_D2_PIN                        169
+#define  BXT_SDIO_D3_PIN                        170
+#define  BXT_SDIO_CMD_PIN                       171
+#define  BXT_SDCARD_CLK_PIN                     172
+#define  BXT_SDCARD_D0_PIN                      173
+#define  BXT_SDCARD_D1_PIN                      174
+#define  BXT_SDCARD_D2_PIN                      175
+#define  BXT_SDCARD_D3_PIN                      176
+#define  BXT_SDCARD_CD_B_PIN                    177
+#define  BXT_SDCARD_CMD_PIN                     178
+#define  BXT_SDCARD_LVL_CLK_FB_PIN              179
+#define  BXT_SDCARD_LVL_CMD_DIR_PIN             180
+#define  BXT_SDCARD_LVL_DAT_DIR_PIN             181
+#define  BXT_EMMC0_STROBE_PIN                   182
+#define  BXT_SDIO_PWR_DOWN_B_PIN                183
+#define  BXT_SDCARD_PWR_DOWN_B_PIN              184
+#define  BXT_SDCARD_LVL_SEL_PIN                 185
+#define  BXT_SDCARD_LVL_WP_PIN                  186
+#define  BXT_LPSS_I2C0_SDA_PIN                  124
+#define  BXT_LPSS_I2C0_SCL_PIN                  125
+#define  BXT_LPSS_I2C1_SDA_PIN                  126
+#define  BXT_LPSS_I2C1_SCL_PIN                  127
+#define  BXT_LPSS_I2C2_SDA_PIN                  128
+#define  BXT_LPSS_I2C2_SCL_PIN                  129
+#define  BXT_LPSS_I2C3_SDA_PIN                  130
+#define  BXT_LPSS_I2C3_SCL_PIN                  131
+#define  BXT_LPSS_I2C4_SDA_PIN                  132
+#define  BXT_LPSS_I2C4_SCL_PIN                  133
+#define  BXT_LPSS_I2C5_SDA_PIN                  134
+#define  BXT_LPSS_I2C5_SCL_PIN                  135
+#define  BXT_LPSS_I2C6_SDA_PIN                  136
+#define  BXT_LPSS_I2C6_SCL_PIN                  137
+#define  BXT_LPSS_I2C7_SDA_PIN                  138
+#define  BXT_LPSS_I2C7_SCL_PIN                  139
+#define  BXT_ISH_I2C0_SDA_PIN                   140
+#define  BXT_ISH_I2C0_SCL_PIN                   141
+#define  BXT_ISH_I2C1_SDA_PIN                   142
+#define  BXT_ISH_I2C1_SCL_PIN                   143
+#define  BXT_ISH_I2C2_SDA_PIN                   144
+#define  BXT_ISH_I2C2_SCL_PIN                   145
+#define  BXT_ISH_GPIO_0_PIN                     146
+#define  BXT_ISH_GPIO_1_PIN                     147
+#define  BXT_ISH_GPIO_2_PIN                     148
+#define  BXT_ISH_GPIO_3_PIN                     149
+#define  BXT_ISH_GPIO_4_PIN                     150
+#define  BXT_ISH_GPIO_5_PIN                     151
+#define  BXT_ISH_GPIO_6_PIN                     152
+#define  BXT_ISH_GPIO_7_PIN                     153
+#define  BXT_ISH_GPIO_8_PIN                     154
+#define  BXT_ISH_GPIO_9_PIN                     155
+#define  BXT_AVS_I2S1_MCLK_PIN                  74
+#define  BXT_AVS_I2S1_BCLK_PIN                  75
+#define  BXT_AVS_I2S1_WS_SYNC_PIN               76
+#define  BXT_AVS_I2S1_SDI_PIN                   77
+#define  BXT_AVS_I2S1_SDO_PIN                   78
+#define  BXT_AVS_M_CLK_A1_PIN                   79
+#define  BXT_AVS_M_CLK_B1_PIN                   80
+#define  BXT_AVS_M_DATA_1_PIN                   81
+#define  BXT_AVS_M_CLK_AB2_PIN                  82
+#define  BXT_AVS_M_DATA_2_PIN                   83
+#define  BXT_AVS_I2S2_MCLK_PIN                  84
+#define  BXT_AVS_I2S2_BCLK_PIN                  85
+#define  BXT_AVS_I2S2_WS_SYNC_PIN               86
+#define  BXT_AVS_I2S2_SDI_PIN                   87
+#define  BXT_AVS_I2S2_SDO_PIN                   88
+#define  BXT_AVS_I2S3_BCLK_PIN                  89
+#define  BXT_AVS_I2S3_WS_SYNC_PIN               90
+#define  BXT_AVS_I2S3_SDI_PIN                   91
+#define  BXT_AVS_I2S3_SDO_PIN                   92
+#define  BXT_AVS_I2S4_BCLK_PIN                  93
+#define  BXT_AVS_I2S4_WS_SYNC_PIN               94
+#define  BXT_AVS_I2S4_SDI_PIN                   95
+#define  BXT_AVS_I2S4_SDO_PIN                   96
+#define  BXT_FST_SPI_CS0_B_PIN                  97
+#define  BXT_FST_SPI_CS1_B_PIN                  98
+#define  BXT_FST_SPI_MOSI_IO0_PIN               99
+#define  BXT_FST_SPI_MISO_IO1_PIN               100
+#define  BXT_FST_SPI_IO2_PIN                    101
+#define  BXT_FST_SPI_IO3_PIN                    102
+#define  BXT_FST_SPI_CLK_PIN                    103
+#define  BXT_GP_SSP_0_CLK_PIN                   104
+#define  BXT_GP_SSP_0_FS0_PIN                   105
+#define  BXT_GP_SSP_0_FS1_PIN                   106
+#define  BXT_GP_SSP_0_FS2_PIN                   107
+#define  BXT_GP_SSP_0_RXD_PIN                   109
+#define  BXT_GP_SSP_0_TXD_PIN                   110
+#define  BXT_GP_SSP_1_CLK_PIN                   111
+#define  BXT_GP_SSP_1_FS0_PIN                   112
+#define  BXT_GP_SSP_1_FS1_PIN                   113
+#define  BXT_GP_SSP_1_FS2_PIN                   114
+#define  BXT_GP_SSP_1_FS3_PIN                   115
+#define  BXT_GP_SSP_1_RXD_PIN                   116
+#define  BXT_GP_SSP_1_TXD_PIN                   117
+#define  BXT_GP_SSP_2_CLK_PIN                   118
+#define  BXT_GP_SSP_2_FS0_PIN                   119
+#define  BXT_GP_SSP_2_FS1_PIN                   120
+#define  BXT_GP_SSP_2_FS2_PIN                   121
+#define  BXT_GP_SSP_2_RXD_PIN                   122
+#define  BXT_GP_SSP_2_TXD_PIN                   123
+#define  BXT_TRACE_0_CLK_VNN_PIN                0
+#define  BXT_TRACE_0_DATA0_VNN_PIN              1
+#define  BXT_TRACE_0_DATA1_VNN_PIN              2
+#define  BXT_TRACE_0_DATA2_VNN_PIN              3
+#define  BXT_TRACE_0_DATA3_VNN_PIN              4
+#define  BXT_TRACE_0_DATA4_VNN_PIN              5
+#define  BXT_TRACE_0_DATA5_VNN_PIN              6
+#define  BXT_TRACE_0_DATA6_VNN_PIN              7
+#define  BXT_TRACE_0_DATA7_VNN_PIN              8
+#define  BXT_TRACE_1_CLK_VNN_PIN                9
+#define  BXT_TRACE_1_DATA0_VNN_PIN              10
+#define  BXT_TRACE_1_DATA1_VNN_PIN              11
+#define  BXT_TRACE_1_DATA2_VNN_PIN              12
+#define  BXT_TRACE_1_DATA3_VNN_PIN              13
+#define  BXT_TRACE_1_DATA4_VNN_PIN              14
+#define  BXT_TRACE_1_DATA5_VNN_PIN              15
+#define  BXT_TRACE_1_DATA6_VNN_PIN              16
+#define  BXT_TRACE_1_DATA7_VNN_PIN              17
+#define  BXT_TRACE_2_CLK_VNN_PIN                18
+#define  BXT_TRACE_2_DATA0_VNN_PIN              19
+#define  BXT_TRACE_2_DATA1_VNN_PIN              20
+#define  BXT_TRACE_2_DATA2_VNN_PIN              21
+#define  BXT_TRACE_2_DATA3_VNN_PIN              22
+#define  BXT_TRACE_2_DATA4_VNN_PIN              23
+#define  BXT_TRACE_2_DATA5_VNN_PIN              24
+#define  BXT_TRACE_2_DATA6_VNN_PIN              25
+#define  BXT_TRACE_2_DATA7_VNN_PIN              26
+#define  BXT_TRIGOUT_0_PIN                      27
+#define  BXT_TRIGOUT_1_PIN                      28
+#define  BXT_TRIGIN_0_PIN                       29
+#define  BXT_SEC_TCK_PIN                        30
+#define  BXT_SEC_TDI_PIN                        31
+#define  BXT_SEC_TMS_PIN                        32
+#define  BXT_SEC_TDO_PIN                        33
+#define  BXT_PWM0_PIN                           34
+#define  BXT_PWM1_PIN                           35
+#define  BXT_PWM2_PIN                           36
+#define  BXT_PWM3_PIN                           37
+#define  BXT_LPSS_UART0_RXD_PIN                 38
+#define  BXT_LPSS_UART0_TXD_PIN                 39
+#define  BXT_LPSS_UART0_RTS_B_PIN               40
+#define  BXT_LPSS_UART0_CTS_B_PIN               41
+#define  BXT_LPSS_UART1_RXD_PIN                 42
+#define  BXT_LPSS_UART1_TXD_PIN                 43
+#define  BXT_LPSS_UART1_RTS_B_PIN               44
+#define  BXT_LPSS_UART1_CTS_B_PIN               45
+#define  BXT_LPSS_UART2_RXD_PIN                 46
+#define  BXT_LPSS_UART2_TXD_PIN                 47
+#define  BXT_LPSS_UART2_RTS_B_PIN               48
+#define  BXT_LPSS_UART2_CTS_B_PIN               49
+#define  BXT_ISH_UART0_RXD_PIN                  50
+#define  BXT_ISH_UART0_TXD_PIN                  51
+#define  BXT_ISH_UART0_RTS_B_PIN                52
+#define  BXT_ISH_UART0_CTS_B_PIN                53
+#define  BXT_ISH_UART1_RXD_PIN                  54
+#define  BXT_ISH_UART1_TXD_PIN                  55
+#define  BXT_ISH_UART1_RTS_B_PIN                56
+#define  BXT_ISH_UART1_CTS_B_PIN                57
+#define  BXT_ISH_UART2_RXD_PIN                  58
+#define  BXT_ISH_UART2_TXD_PIN                  59
+#define  BXT_ISH_UART2_RTS_B_PIN                60
+#define  BXT_ISH_UART2_CTS_B_PIN                61
+#define  BXT_GP_CAMERASB00_PIN                  62
+#define  BXT_GP_CAMERASB01_PIN                  63
+#define  BXT_GP_CAMERASB02_PIN                  64
+#define  BXT_GP_CAMERASB03_PIN                  65
+#define  BXT_GP_CAMERASB04_PIN                  66
+#define  BXT_GP_CAMERASB05_PIN                  67
+#define  BXT_GP_CAMERASB06_PIN                  68
+#define  BXT_GP_CAMERASB07_PIN                  69
+#define  BXT_GP_CAMERASB08_PIN                  70
+#define  BXT_GP_CAMERASB09_PIN                  71
+#define  BXT_GP_CAMERASB10_PIN                  72
+#define  BXT_GP_CAMERASB11_PIN                  73
+
+#define  BXT_HV_DDI0_DDC_SDA_OFFSET             264
+#define  BXT_HV_DDI0_DDC_SCL_OFFSET             265
+#define  BXT_HV_DDI1_DDC_SDA_OFFSET             266
+#define  BXT_HV_DDI1_DDC_SCL_OFFSET             267
+#define  BXT_DBI_SDA_OFFSET             268
+#define  BXT_DBI_SCL_OFFSET             269
+#define  BXT_PANEL0_VDDEN_OFFSET                270
+#define  BXT_PANEL0_BKLTEN_OFFSET               271
+#define  BXT_PANEL0_BKLTCTL_OFFSET              272
+#define  BXT_PANEL1_VDDEN_OFFSET                273
+#define  BXT_PANEL1_BKLTEN_OFFSET               274
+#define  BXT_PANEL1_BKLTCTL_OFFSET              275
+#define  BXT_DBI_CSX_OFFSET             276
+#define  BXT_DBI_RESX_OFFSET            277
+#define  BXT_GP_INTD_DSI_TE1_OFFSET             278
+#define  BXT_GP_INTD_DSI_TE2_OFFSET             279
+#define  BXT_USB_OC0_B_OFFSET           280
+#define  BXT_USB_OC1_B_OFFSET           281
+#define  BXT_MEX_WAKE0_B_OFFSET         282
+#define  BXT_MEX_WAKE1_B_OFFSET         283
+#define  BXT_EMMC0_CLK_OFFSET           284
+#define  BXT_EMMC0_D0_OFFSET            285
+#define  BXT_EMMC0_D1_OFFSET            286
+#define  BXT_EMMC0_D2_OFFSET            287
+#define  BXT_EMMC0_D3_OFFSET            288
+#define  BXT_EMMC0_D4_OFFSET            289
+#define  BXT_EMMC0_D5_OFFSET            290
+#define  BXT_EMMC0_D6_OFFSET            291
+#define  BXT_EMMC0_D7_OFFSET            292
+#define  BXT_EMMC0_CMD_OFFSET           293
+#define  BXT_SDIO_CLK_OFFSET            294
+#define  BXT_SDIO_D0_OFFSET             295
+#define  BXT_SDIO_D1_OFFSET             296
+#define  BXT_SDIO_D2_OFFSET             297
+#define  BXT_SDIO_D3_OFFSET             298
+#define  BXT_SDIO_CMD_OFFSET            299
+#define  BXT_SDCARD_CLK_OFFSET          300
+#define  BXT_SDCARD_D0_OFFSET           301
+#define  BXT_SDCARD_D1_OFFSET           302
+#define  BXT_SDCARD_D2_OFFSET           303
+#define  BXT_SDCARD_D3_OFFSET           304
+#define  BXT_SDCARD_CD_B_OFFSET         305
+#define  BXT_SDCARD_CMD_OFFSET          306
+#define  BXT_SDCARD_LVL_CLK_FB_OFFSET           307
+#define  BXT_SDCARD_LVL_CMD_DIR_OFFSET          308
+#define  BXT_SDCARD_LVL_DAT_DIR_OFFSET          309
+#define  BXT_EMMC0_STROBE_OFFSET                310
+#define  BXT_SDIO_PWR_DOWN_B_OFFSET             311
+#define  BXT_SDCARD_PWR_DOWN_B_OFFSET           312
+#define  BXT_SDCARD_LVL_SEL_OFFSET              313
+#define  BXT_SDCARD_LVL_WP_OFFSET               314
+#define  BXT_LPSS_I2C0_SDA_OFFSET               315
+#define  BXT_LPSS_I2C0_SCL_OFFSET               316
+#define  BXT_LPSS_I2C1_SDA_OFFSET               317
+#define  BXT_LPSS_I2C1_SCL_OFFSET               318
+#define  BXT_LPSS_I2C2_SDA_OFFSET               319
+#define  BXT_LPSS_I2C2_SCL_OFFSET               320
+#define  BXT_LPSS_I2C3_SDA_OFFSET               321
+#define  BXT_LPSS_I2C3_SCL_OFFSET               322
+#define  BXT_LPSS_I2C4_SDA_OFFSET               323
+#define  BXT_LPSS_I2C4_SCL_OFFSET               324
+#define  BXT_LPSS_I2C5_SDA_OFFSET               325
+#define  BXT_LPSS_I2C5_SCL_OFFSET               326
+#define  BXT_LPSS_I2C6_SDA_OFFSET               327
+#define  BXT_LPSS_I2C6_SCL_OFFSET               328
+#define  BXT_LPSS_I2C7_SDA_OFFSET               329
+#define  BXT_LPSS_I2C7_SCL_OFFSET               330
+#define  BXT_ISH_I2C0_SDA_OFFSET                331
+#define  BXT_ISH_I2C0_SCL_OFFSET                332
+#define  BXT_ISH_I2C1_SDA_OFFSET                333
+#define  BXT_ISH_I2C1_SCL_OFFSET                334
+#define  BXT_ISH_I2C2_SDA_OFFSET                335
+#define  BXT_ISH_I2C2_SCL_OFFSET                336
+#define  BXT_ISH_GPIO_0_OFFSET          337
+#define  BXT_ISH_GPIO_1_OFFSET          338
+#define  BXT_ISH_GPIO_2_OFFSET          339
+#define  BXT_ISH_GPIO_3_OFFSET          340
+#define  BXT_ISH_GPIO_4_OFFSET          341
+#define  BXT_ISH_GPIO_5_OFFSET          342
+#define  BXT_ISH_GPIO_6_OFFSET          343
+#define  BXT_ISH_GPIO_7_OFFSET          344
+#define  BXT_ISH_GPIO_8_OFFSET          345
+#define  BXT_ISH_GPIO_9_OFFSET          346
+#define  BXT_AVS_I2S1_MCLK_OFFSET               378
+#define  BXT_AVS_I2S1_BCLK_OFFSET               379
+#define  BXT_AVS_I2S1_WS_SYNC_OFFSET            380
+#define  BXT_AVS_I2S1_SDI_OFFSET                381
+#define  BXT_AVS_I2S1_SDO_OFFSET                382
+#define  BXT_AVS_M_CLK_A1_OFFSET                383
+#define  BXT_AVS_M_CLK_B1_OFFSET                384
+#define  BXT_AVS_M_DATA_1_OFFSET                385
+#define  BXT_AVS_M_CLK_AB2_OFFSET               386
+#define  BXT_AVS_M_DATA_2_OFFSET                387
+#define  BXT_AVS_I2S2_MCLK_OFFSET               388
+#define  BXT_AVS_I2S2_BCLK_OFFSET               389
+#define  BXT_AVS_I2S2_WS_SYNC_OFFSET            390
+#define  BXT_AVS_I2S2_SDI_OFFSET                391
+#define  BXT_AVS_I2S2_SDO_OFFSET                392
+#define  BXT_AVS_I2S3_BCLK_OFFSET               393
+#define  BXT_AVS_I2S3_WS_SYNC_OFFSET            394
+#define  BXT_AVS_I2S3_SDI_OFFSET                395
+#define  BXT_AVS_I2S3_SDO_OFFSET                396
+#define  BXT_AVS_I2S4_BCLK_OFFSET               397
+#define  BXT_AVS_I2S4_WS_SYNC_OFFSET            398
+#define  BXT_AVS_I2S4_SDI_OFFSET                399
+#define  BXT_AVS_I2S4_SDO_OFFSET                400
+#define  BXT_FST_SPI_CS0_B_OFFSET               402
+#define  BXT_FST_SPI_CS1_B_OFFSET               403
+#define  BXT_FST_SPI_MOSI_IO0_OFFSET            404
+#define  BXT_FST_SPI_MISO_IO1_OFFSET            405
+#define  BXT_FST_SPI_IO2_OFFSET         406
+#define  BXT_FST_SPI_IO3_OFFSET         407
+#define  BXT_FST_SPI_CLK_OFFSET         408
+#define  BXT_GP_SSP_0_CLK_OFFSET                410
+#define  BXT_GP_SSP_0_FS0_OFFSET                411
+#define  BXT_GP_SSP_0_FS1_OFFSET                412
+#define  BXT_GP_SSP_0_FS2_OFFSET                413
+#define  BXT_GP_SSP_0_RXD_OFFSET                414
+#define  BXT_GP_SSP_0_TXD_OFFSET                415
+#define  BXT_GP_SSP_1_CLK_OFFSET                416
+#define  BXT_GP_SSP_1_FS0_OFFSET                417
+#define  BXT_GP_SSP_1_FS1_OFFSET                418
+#define  BXT_GP_SSP_1_FS2_OFFSET                419
+#define  BXT_GP_SSP_1_FS3_OFFSET                420
+#define  BXT_GP_SSP_1_RXD_OFFSET                421
+#define  BXT_GP_SSP_1_TXD_OFFSET                422
+#define  BXT_GP_SSP_2_CLK_OFFSET                423
+#define  BXT_GP_SSP_2_FS0_OFFSET                424
+#define  BXT_GP_SSP_2_FS1_OFFSET                425
+#define  BXT_GP_SSP_2_FS2_OFFSET                426
+#define  BXT_GP_SSP_2_RXD_OFFSET                427
+#define  BXT_GP_SSP_2_TXD_OFFSET                428
+#define  BXT_TRACE_0_CLK_VNN_OFFSET             429
+#define  BXT_TRACE_0_DATA0_VNN_OFFSET           430
+#define  BXT_TRACE_0_DATA1_VNN_OFFSET           431
+#define  BXT_TRACE_0_DATA2_VNN_OFFSET           432
+#define  BXT_TRACE_0_DATA3_VNN_OFFSET           433
+#define  BXT_TRACE_0_DATA4_VNN_OFFSET           434
+#define  BXT_TRACE_0_DATA5_VNN_OFFSET           435
+#define  BXT_TRACE_0_DATA6_VNN_OFFSET           436
+#define  BXT_TRACE_0_DATA7_VNN_OFFSET           437
+#define  BXT_TRACE_1_CLK_VNN_OFFSET             438
+#define  BXT_TRACE_1_DATA0_VNN_OFFSET           439
+#define  BXT_TRACE_1_DATA1_VNN_OFFSET           440
+#define  BXT_TRACE_1_DATA2_VNN_OFFSET           441
+#define  BXT_TRACE_1_DATA3_VNN_OFFSET           442
+#define  BXT_TRACE_1_DATA4_VNN_OFFSET           443
+#define  BXT_TRACE_1_DATA5_VNN_OFFSET           444
+#define  BXT_TRACE_1_DATA6_VNN_OFFSET           445
+#define  BXT_TRACE_1_DATA7_VNN_OFFSET           446
+#define  BXT_TRACE_2_CLK_VNN_OFFSET             447
+#define  BXT_TRACE_2_DATA0_VNN_OFFSET           448
+#define  BXT_TRACE_2_DATA1_VNN_OFFSET           449
+#define  BXT_TRACE_2_DATA2_VNN_OFFSET           450
+#define  BXT_TRACE_2_DATA3_VNN_OFFSET           451
+#define  BXT_TRACE_2_DATA4_VNN_OFFSET           452
+#define  BXT_TRACE_2_DATA5_VNN_OFFSET           453
+#define  BXT_TRACE_2_DATA6_VNN_OFFSET           454
+#define  BXT_TRACE_2_DATA7_VNN_OFFSET           455
+#define  BXT_TRIGOUT_0_OFFSET           456
+#define  BXT_TRIGOUT_1_OFFSET           457
+#define  BXT_TRIGIN_0_OFFSET            458
+#define  BXT_SEC_TCK_OFFSET             459
+#define  BXT_SEC_TDI_OFFSET             460
+#define  BXT_SEC_TMS_OFFSET             461
+#define  BXT_SEC_TDO_OFFSET             462
+#define  BXT_PWM0_OFFSET                463
+#define  BXT_PWM1_OFFSET                464
+#define  BXT_PWM2_OFFSET                465
+#define  BXT_PWM3_OFFSET                466
+#define  BXT_LPSS_UART0_RXD_OFFSET              467
+#define  BXT_LPSS_UART0_TXD_OFFSET              468
+#define  BXT_LPSS_UART0_RTS_B_OFFSET            469
+#define  BXT_LPSS_UART0_CTS_B_OFFSET            470
+#define  BXT_LPSS_UART1_RXD_OFFSET              471
+#define  BXT_LPSS_UART1_TXD_OFFSET              472
+#define  BXT_LPSS_UART1_RTS_B_OFFSET            473
+#define  BXT_LPSS_UART1_CTS_B_OFFSET            474
+#define  BXT_LPSS_UART2_RXD_OFFSET              475
+#define  BXT_LPSS_UART2_TXD_OFFSET              476
+#define  BXT_LPSS_UART2_RTS_B_OFFSET            477
+#define  BXT_LPSS_UART2_CTS_B_OFFSET            478
+#define  BXT_ISH_UART0_RXD_OFFSET               479
+#define  BXT_ISH_UART0_TXD_OFFSET               480
+#define  BXT_ISH_UART0_RTS_B_OFFSET             481
+#define  BXT_ISH_UART0_CTS_B_OFFSET             482
+#define  BXT_ISH_UART1_RXD_OFFSET               483
+#define  BXT_ISH_UART1_TXD_OFFSET               484
+#define  BXT_ISH_UART1_RTS_B_OFFSET             485
+#define  BXT_ISH_UART1_CTS_B_OFFSET             486
+#define  BXT_ISH_UART2_RXD_OFFSET               487
+#define  BXT_ISH_UART2_TXD_OFFSET               488
+#define  BXT_ISH_UART2_RTS_B_OFFSET             489
+#define  BXT_ISH_UART2_CTS_B_OFFSET             490
+#define  BXT_GP_CAMERASB00_OFFSET               491
+#define  BXT_GP_CAMERASB01_OFFSET               492
+#define  BXT_GP_CAMERASB02_OFFSET               493
+#define  BXT_GP_CAMERASB03_OFFSET               494
+#define  BXT_GP_CAMERASB04_OFFSET               495
+#define  BXT_GP_CAMERASB05_OFFSET               496
+#define  BXT_GP_CAMERASB06_OFFSET               497
+#define  BXT_GP_CAMERASB07_OFFSET               498
+#define  BXT_GP_CAMERASB08_OFFSET               499
+#define  BXT_GP_CAMERASB09_OFFSET               500
+#define  BXT_GP_CAMERASB10_OFFSET               501
+#define  BXT_GP_CAMERASB11_OFFSET               502
+
+static struct bxt_gpio_table bxt_gtable[] = {
+	{BXT_HV_DDI0_DDC_SDA_PIN, BXT_HV_DDI0_DDC_SDA_OFFSET},
+	{BXT_HV_DDI0_DDC_SCL_PIN, BXT_HV_DDI0_DDC_SCL_OFFSET},
+	{BXT_HV_DDI1_DDC_SDA_PIN, BXT_HV_DDI1_DDC_SDA_OFFSET},
+	{BXT_HV_DDI1_DDC_SCL_PIN, BXT_HV_DDI1_DDC_SCL_OFFSET},
+	{BXT_DBI_SDA_PIN, BXT_DBI_SDA_OFFSET},
+	{BXT_DBI_SCL_PIN, BXT_DBI_SCL_OFFSET},
+	{BXT_PANEL0_VDDEN_PIN, BXT_PANEL0_VDDEN_OFFSET},
+	{BXT_PANEL0_BKLTEN_PIN, BXT_PANEL0_BKLTEN_OFFSET},
+	{BXT_PANEL0_BKLTCTL_PIN, BXT_PANEL0_BKLTCTL_OFFSET},
+	{BXT_PANEL1_VDDEN_PIN, BXT_PANEL1_VDDEN_OFFSET},
+	{BXT_PANEL1_BKLTEN_PIN, BXT_PANEL1_BKLTEN_OFFSET},
+	{BXT_PANEL1_BKLTCTL_PIN, BXT_PANEL1_BKLTCTL_OFFSET},
+	{BXT_DBI_CSX_PIN, BXT_DBI_CSX_OFFSET},
+	{BXT_DBI_RESX_PIN, BXT_DBI_RESX_OFFSET},
+	{BXT_GP_INTD_DSI_TE1_PIN, BXT_GP_INTD_DSI_TE1_OFFSET},
+	{BXT_GP_INTD_DSI_TE2_PIN, BXT_GP_INTD_DSI_TE2_OFFSET},
+	{BXT_USB_OC0_B_PIN, BXT_USB_OC0_B_OFFSET},
+	{BXT_USB_OC1_B_PIN, BXT_USB_OC1_B_OFFSET},
+	{BXT_MEX_WAKE0_B_PIN, BXT_MEX_WAKE0_B_OFFSET},
+	{BXT_MEX_WAKE1_B_PIN, BXT_MEX_WAKE1_B_OFFSET},
+	{BXT_EMMC0_CLK_PIN, BXT_EMMC0_CLK_OFFSET},
+	{BXT_EMMC0_D0_PIN, BXT_EMMC0_D0_OFFSET},
+	{BXT_EMMC0_D1_PIN, BXT_EMMC0_D1_OFFSET},
+	{BXT_EMMC0_D2_PIN, BXT_EMMC0_D2_OFFSET},
+	{BXT_EMMC0_D3_PIN, BXT_EMMC0_D3_OFFSET},
+	{BXT_EMMC0_D4_PIN, BXT_EMMC0_D4_OFFSET},
+	{BXT_EMMC0_D5_PIN, BXT_EMMC0_D5_OFFSET},
+	{BXT_EMMC0_D6_PIN, BXT_EMMC0_D6_OFFSET},
+	{BXT_EMMC0_D7_PIN, BXT_EMMC0_D7_OFFSET},
+	{BXT_EMMC0_CMD_PIN, BXT_EMMC0_CMD_OFFSET},
+	{BXT_SDIO_CLK_PIN, BXT_SDIO_CLK_OFFSET},
+	{BXT_SDIO_D0_PIN, BXT_SDIO_D0_OFFSET},
+	{BXT_SDIO_D1_PIN, BXT_SDIO_D1_OFFSET},
+	{BXT_SDIO_D2_PIN, BXT_SDIO_D2_OFFSET},
+	{BXT_SDIO_D3_PIN, BXT_SDIO_D3_OFFSET},
+	{BXT_SDIO_CMD_PIN, BXT_SDIO_CMD_OFFSET},
+	{BXT_SDCARD_CLK_PIN, BXT_SDCARD_CLK_OFFSET},
+	{BXT_SDCARD_D0_PIN, BXT_SDCARD_D0_OFFSET},
+	{BXT_SDCARD_D1_PIN, BXT_SDCARD_D1_OFFSET},
+	{BXT_SDCARD_D2_PIN, BXT_SDCARD_D2_OFFSET},
+	{BXT_SDCARD_D3_PIN, BXT_SDCARD_D3_OFFSET},
+	{BXT_SDCARD_CD_B_PIN, BXT_SDCARD_CD_B_OFFSET},
+	{BXT_SDCARD_CMD_PIN, BXT_SDCARD_CMD_OFFSET},
+	{BXT_SDCARD_LVL_CLK_FB_PIN, BXT_SDCARD_LVL_CLK_FB_OFFSET},
+	{BXT_SDCARD_LVL_CMD_DIR_PIN, BXT_SDCARD_LVL_CMD_DIR_OFFSET},
+	{BXT_SDCARD_LVL_DAT_DIR_PIN, BXT_SDCARD_LVL_DAT_DIR_OFFSET},
+	{BXT_EMMC0_STROBE_PIN, BXT_EMMC0_STROBE_OFFSET},
+	{BXT_SDIO_PWR_DOWN_B_PIN, BXT_SDIO_PWR_DOWN_B_OFFSET},
+	{BXT_SDCARD_PWR_DOWN_B_PIN, BXT_SDCARD_PWR_DOWN_B_OFFSET},
+	{BXT_SDCARD_LVL_SEL_PIN, BXT_SDCARD_LVL_SEL_OFFSET},
+	{BXT_SDCARD_LVL_WP_PIN, BXT_SDCARD_LVL_WP_OFFSET},
+	{BXT_LPSS_I2C0_SDA_PIN, BXT_LPSS_I2C0_SDA_OFFSET},
+	{BXT_LPSS_I2C0_SCL_PIN, BXT_LPSS_I2C0_SCL_OFFSET},
+	{BXT_LPSS_I2C1_SDA_PIN, BXT_LPSS_I2C1_SDA_OFFSET},
+	{BXT_LPSS_I2C1_SCL_PIN, BXT_LPSS_I2C1_SCL_OFFSET},
+	{BXT_LPSS_I2C2_SDA_PIN, BXT_LPSS_I2C2_SDA_OFFSET},
+	{BXT_LPSS_I2C2_SCL_PIN, BXT_LPSS_I2C2_SCL_OFFSET},
+	{BXT_LPSS_I2C3_SDA_PIN, BXT_LPSS_I2C3_SDA_OFFSET},
+	{BXT_LPSS_I2C3_SCL_PIN, BXT_LPSS_I2C3_SCL_OFFSET},
+	{BXT_LPSS_I2C4_SDA_PIN, BXT_LPSS_I2C4_SDA_OFFSET},
+	{BXT_LPSS_I2C4_SCL_PIN, BXT_LPSS_I2C4_SCL_OFFSET},
+	{BXT_LPSS_I2C5_SDA_PIN, BXT_LPSS_I2C5_SDA_OFFSET},
+	{BXT_LPSS_I2C5_SCL_PIN, BXT_LPSS_I2C5_SCL_OFFSET},
+	{BXT_LPSS_I2C6_SDA_PIN, BXT_LPSS_I2C6_SDA_OFFSET},
+	{BXT_LPSS_I2C6_SCL_PIN, BXT_LPSS_I2C6_SCL_OFFSET},
+	{BXT_LPSS_I2C7_SDA_PIN, BXT_LPSS_I2C7_SDA_OFFSET},
+	{BXT_LPSS_I2C7_SCL_PIN, BXT_LPSS_I2C7_SCL_OFFSET},
+	{BXT_ISH_I2C0_SDA_PIN, BXT_ISH_I2C0_SDA_OFFSET},
+	{BXT_ISH_I2C0_SCL_PIN, BXT_ISH_I2C0_SCL_OFFSET},
+	{BXT_ISH_I2C1_SDA_PIN, BXT_ISH_I2C1_SDA_OFFSET},
+	{BXT_ISH_I2C1_SCL_PIN, BXT_ISH_I2C1_SCL_OFFSET},
+	{BXT_ISH_I2C2_SDA_PIN, BXT_ISH_I2C2_SDA_OFFSET},
+	{BXT_ISH_I2C2_SCL_PIN, BXT_ISH_I2C2_SCL_OFFSET},
+	{BXT_ISH_GPIO_0_PIN, BXT_ISH_GPIO_0_OFFSET},
+	{BXT_ISH_GPIO_1_PIN, BXT_ISH_GPIO_1_OFFSET},
+	{BXT_ISH_GPIO_2_PIN, BXT_ISH_GPIO_2_OFFSET},
+	{BXT_ISH_GPIO_3_PIN, BXT_ISH_GPIO_3_OFFSET},
+	{BXT_ISH_GPIO_4_PIN, BXT_ISH_GPIO_4_OFFSET},
+	{BXT_ISH_GPIO_5_PIN, BXT_ISH_GPIO_5_OFFSET},
+	{BXT_ISH_GPIO_6_PIN, BXT_ISH_GPIO_6_OFFSET},
+	{BXT_ISH_GPIO_7_PIN, BXT_ISH_GPIO_7_OFFSET},
+	{BXT_ISH_GPIO_8_PIN, BXT_ISH_GPIO_8_OFFSET},
+	{BXT_ISH_GPIO_9_PIN, BXT_ISH_GPIO_9_OFFSET},
+	{BXT_AVS_I2S1_MCLK_PIN, BXT_AVS_I2S1_MCLK_OFFSET},
+	{BXT_AVS_I2S1_BCLK_PIN, BXT_AVS_I2S1_BCLK_OFFSET},
+	{BXT_AVS_I2S1_WS_SYNC_PIN, BXT_AVS_I2S1_WS_SYNC_OFFSET},
+	{BXT_AVS_I2S1_SDI_PIN, BXT_AVS_I2S1_SDI_OFFSET},
+	{BXT_AVS_I2S1_SDO_PIN, BXT_AVS_I2S1_SDO_OFFSET},
+	{BXT_AVS_M_CLK_A1_PIN, BXT_AVS_M_CLK_A1_OFFSET},
+	{BXT_AVS_M_CLK_B1_PIN, BXT_AVS_M_CLK_B1_OFFSET},
+	{BXT_AVS_M_DATA_1_PIN, BXT_AVS_M_DATA_1_OFFSET},
+	{BXT_AVS_M_CLK_AB2_PIN, BXT_AVS_M_CLK_AB2_OFFSET},
+	{BXT_AVS_M_DATA_2_PIN, BXT_AVS_M_DATA_2_OFFSET},
+	{BXT_AVS_I2S2_MCLK_PIN, BXT_AVS_I2S2_MCLK_OFFSET},
+	{BXT_AVS_I2S2_BCLK_PIN, BXT_AVS_I2S2_BCLK_OFFSET},
+	{BXT_AVS_I2S2_WS_SYNC_PIN, BXT_AVS_I2S2_WS_SYNC_OFFSET},
+	{BXT_AVS_I2S2_SDI_PIN, BXT_AVS_I2S2_SDI_OFFSET},
+	{BXT_AVS_I2S2_SDO_PIN, BXT_AVS_I2S2_SDO_OFFSET},
+	{BXT_AVS_I2S3_BCLK_PIN, BXT_AVS_I2S3_BCLK_OFFSET},
+	{BXT_AVS_I2S3_WS_SYNC_PIN, BXT_AVS_I2S3_WS_SYNC_OFFSET},
+	{BXT_AVS_I2S3_SDI_PIN, BXT_AVS_I2S3_SDI_OFFSET},
+	{BXT_AVS_I2S3_SDO_PIN, BXT_AVS_I2S3_SDO_OFFSET},
+	{BXT_AVS_I2S4_BCLK_PIN, BXT_AVS_I2S4_BCLK_OFFSET},
+	{BXT_AVS_I2S4_WS_SYNC_PIN, BXT_AVS_I2S4_WS_SYNC_OFFSET},
+	{BXT_AVS_I2S4_SDI_PIN, BXT_AVS_I2S4_SDI_OFFSET},
+	{BXT_AVS_I2S4_SDO_PIN, BXT_AVS_I2S4_SDO_OFFSET},
+	{BXT_FST_SPI_CS0_B_PIN, BXT_FST_SPI_CS0_B_OFFSET},
+	{BXT_FST_SPI_CS1_B_PIN, BXT_FST_SPI_CS1_B_OFFSET},
+	{BXT_FST_SPI_MOSI_IO0_PIN, BXT_FST_SPI_MOSI_IO0_OFFSET},
+	{BXT_FST_SPI_MISO_IO1_PIN, BXT_FST_SPI_MISO_IO1_OFFSET},
+	{BXT_FST_SPI_IO2_PIN, BXT_FST_SPI_IO2_OFFSET},
+	{BXT_FST_SPI_IO3_PIN, BXT_FST_SPI_IO3_OFFSET},
+	{BXT_FST_SPI_CLK_PIN, BXT_FST_SPI_CLK_OFFSET},
+	{BXT_GP_SSP_0_CLK_PIN, BXT_GP_SSP_0_CLK_OFFSET},
+	{BXT_GP_SSP_0_FS0_PIN, BXT_GP_SSP_0_FS0_OFFSET},
+	{BXT_GP_SSP_0_FS1_PIN, BXT_GP_SSP_0_FS1_OFFSET},
+	{BXT_GP_SSP_0_FS2_PIN, BXT_GP_SSP_0_FS2_OFFSET},
+	{BXT_GP_SSP_0_RXD_PIN, BXT_GP_SSP_0_RXD_OFFSET},
+	{BXT_GP_SSP_0_TXD_PIN, BXT_GP_SSP_0_TXD_OFFSET},
+	{BXT_GP_SSP_1_CLK_PIN, BXT_GP_SSP_1_CLK_OFFSET},
+	{BXT_GP_SSP_1_FS0_PIN, BXT_GP_SSP_1_FS0_OFFSET},
+	{BXT_GP_SSP_1_FS1_PIN, BXT_GP_SSP_1_FS1_OFFSET},
+	{BXT_GP_SSP_1_FS2_PIN, BXT_GP_SSP_1_FS2_OFFSET},
+	{BXT_GP_SSP_1_FS3_PIN, BXT_GP_SSP_1_FS3_OFFSET},
+	{BXT_GP_SSP_1_RXD_PIN, BXT_GP_SSP_1_RXD_OFFSET},
+	{BXT_GP_SSP_1_TXD_PIN, BXT_GP_SSP_1_TXD_OFFSET},
+	{BXT_GP_SSP_2_CLK_PIN, BXT_GP_SSP_2_CLK_OFFSET},
+	{BXT_GP_SSP_2_FS0_PIN, BXT_GP_SSP_2_FS0_OFFSET},
+	{BXT_GP_SSP_2_FS1_PIN, BXT_GP_SSP_2_FS1_OFFSET},
+	{BXT_GP_SSP_2_FS2_PIN, BXT_GP_SSP_2_FS2_OFFSET},
+	{BXT_GP_SSP_2_RXD_PIN, BXT_GP_SSP_2_RXD_OFFSET},
+	{BXT_GP_SSP_2_TXD_PIN, BXT_GP_SSP_2_TXD_OFFSET},
+	{BXT_TRACE_0_CLK_VNN_PIN, BXT_TRACE_0_CLK_VNN_OFFSET},
+	{BXT_TRACE_0_DATA0_VNN_PIN, BXT_TRACE_0_DATA0_VNN_OFFSET},
+	{BXT_TRACE_0_DATA1_VNN_PIN, BXT_TRACE_0_DATA1_VNN_OFFSET},
+	{BXT_TRACE_0_DATA2_VNN_PIN, BXT_TRACE_0_DATA2_VNN_OFFSET},
+	{BXT_TRACE_0_DATA3_VNN_PIN, BXT_TRACE_0_DATA3_VNN_OFFSET},
+	{BXT_TRACE_0_DATA4_VNN_PIN, BXT_TRACE_0_DATA4_VNN_OFFSET},
+	{BXT_TRACE_0_DATA5_VNN_PIN, BXT_TRACE_0_DATA5_VNN_OFFSET},
+	{BXT_TRACE_0_DATA6_VNN_PIN, BXT_TRACE_0_DATA6_VNN_OFFSET},
+	{BXT_TRACE_0_DATA7_VNN_PIN, BXT_TRACE_0_DATA7_VNN_OFFSET},
+	{BXT_TRACE_1_CLK_VNN_PIN, BXT_TRACE_1_CLK_VNN_OFFSET},
+	{BXT_TRACE_1_DATA0_VNN_PIN, BXT_TRACE_1_DATA0_VNN_OFFSET},
+	{BXT_TRACE_1_DATA1_VNN_PIN, BXT_TRACE_1_DATA1_VNN_OFFSET},
+	{BXT_TRACE_1_DATA2_VNN_PIN, BXT_TRACE_1_DATA2_VNN_OFFSET},
+	{BXT_TRACE_1_DATA3_VNN_PIN, BXT_TRACE_1_DATA3_VNN_OFFSET},
+	{BXT_TRACE_1_DATA4_VNN_PIN, BXT_TRACE_1_DATA4_VNN_OFFSET},
+	{BXT_TRACE_1_DATA5_VNN_PIN, BXT_TRACE_1_DATA5_VNN_OFFSET},
+	{BXT_TRACE_1_DATA6_VNN_PIN, BXT_TRACE_1_DATA6_VNN_OFFSET},
+	{BXT_TRACE_1_DATA7_VNN_PIN, BXT_TRACE_1_DATA7_VNN_OFFSET},
+	{BXT_TRACE_2_CLK_VNN_PIN, BXT_TRACE_2_CLK_VNN_OFFSET},
+	{BXT_TRACE_2_DATA0_VNN_PIN, BXT_TRACE_2_DATA0_VNN_OFFSET},
+	{BXT_TRACE_2_DATA1_VNN_PIN, BXT_TRACE_2_DATA1_VNN_OFFSET},
+	{BXT_TRACE_2_DATA2_VNN_PIN, BXT_TRACE_2_DATA2_VNN_OFFSET},
+	{BXT_TRACE_2_DATA3_VNN_PIN, BXT_TRACE_2_DATA3_VNN_OFFSET},
+	{BXT_TRACE_2_DATA4_VNN_PIN, BXT_TRACE_2_DATA4_VNN_OFFSET},
+	{BXT_TRACE_2_DATA5_VNN_PIN, BXT_TRACE_2_DATA5_VNN_OFFSET},
+	{BXT_TRACE_2_DATA6_VNN_PIN, BXT_TRACE_2_DATA6_VNN_OFFSET},
+	{BXT_TRACE_2_DATA7_VNN_PIN, BXT_TRACE_2_DATA7_VNN_OFFSET},
+	{BXT_TRIGOUT_0_PIN, BXT_TRIGOUT_0_OFFSET},
+	{BXT_TRIGOUT_1_PIN, BXT_TRIGOUT_1_OFFSET},
+	{BXT_TRIGIN_0_PIN, BXT_TRIGIN_0_OFFSET},
+	{BXT_SEC_TCK_PIN, BXT_SEC_TCK_OFFSET},
+	{BXT_SEC_TDI_PIN, BXT_SEC_TDI_OFFSET},
+	{BXT_SEC_TMS_PIN, BXT_SEC_TMS_OFFSET},
+	{BXT_SEC_TDO_PIN, BXT_SEC_TDO_OFFSET},
+	{BXT_PWM0_PIN, BXT_PWM0_OFFSET},
+	{BXT_PWM1_PIN, BXT_PWM1_OFFSET},
+	{BXT_PWM2_PIN, BXT_PWM2_OFFSET},
+	{BXT_PWM3_PIN, BXT_PWM3_OFFSET},
+	{BXT_LPSS_UART0_RXD_PIN, BXT_LPSS_UART0_RXD_OFFSET},
+	{BXT_LPSS_UART0_TXD_PIN, BXT_LPSS_UART0_TXD_OFFSET},
+	{BXT_LPSS_UART0_RTS_B_PIN, BXT_LPSS_UART0_RTS_B_OFFSET},
+	{BXT_LPSS_UART0_CTS_B_PIN, BXT_LPSS_UART0_CTS_B_OFFSET},
+	{BXT_LPSS_UART1_RXD_PIN, BXT_LPSS_UART1_RXD_OFFSET},
+	{BXT_LPSS_UART1_TXD_PIN, BXT_LPSS_UART1_TXD_OFFSET},
+	{BXT_LPSS_UART1_RTS_B_PIN, BXT_LPSS_UART1_RTS_B_OFFSET},
+	{BXT_LPSS_UART1_CTS_B_PIN, BXT_LPSS_UART1_CTS_B_OFFSET},
+	{BXT_LPSS_UART2_RXD_PIN, BXT_LPSS_UART2_RXD_OFFSET},
+	{BXT_LPSS_UART2_TXD_PIN, BXT_LPSS_UART2_TXD_OFFSET},
+	{BXT_LPSS_UART2_RTS_B_PIN, BXT_LPSS_UART2_RTS_B_OFFSET},
+	{BXT_LPSS_UART2_CTS_B_PIN, BXT_LPSS_UART2_CTS_B_OFFSET},
+	{BXT_ISH_UART0_RXD_PIN, BXT_ISH_UART0_RXD_OFFSET},
+	{BXT_ISH_UART0_TXD_PIN, BXT_ISH_UART0_TXD_OFFSET},
+	{BXT_ISH_UART0_RTS_B_PIN, BXT_ISH_UART0_RTS_B_OFFSET},
+	{BXT_ISH_UART0_CTS_B_PIN, BXT_ISH_UART0_CTS_B_OFFSET},
+	{BXT_ISH_UART1_RXD_PIN, BXT_ISH_UART1_RXD_OFFSET},
+	{BXT_ISH_UART1_TXD_PIN, BXT_ISH_UART1_TXD_OFFSET},
+	{BXT_ISH_UART1_RTS_B_PIN, BXT_ISH_UART1_RTS_B_OFFSET},
+	{BXT_ISH_UART1_CTS_B_PIN, BXT_ISH_UART1_CTS_B_OFFSET},
+	{BXT_ISH_UART2_RXD_PIN, BXT_ISH_UART2_RXD_OFFSET},
+	{BXT_ISH_UART2_TXD_PIN, BXT_ISH_UART2_TXD_OFFSET},
+	{BXT_ISH_UART2_RTS_B_PIN, BXT_ISH_UART2_RTS_B_OFFSET},
+	{BXT_ISH_UART2_CTS_B_PIN, BXT_ISH_UART2_CTS_B_OFFSET},
+	{BXT_GP_CAMERASB00_PIN, BXT_GP_CAMERASB00_OFFSET},
+	{BXT_GP_CAMERASB01_PIN, BXT_GP_CAMERASB01_OFFSET},
+	{BXT_GP_CAMERASB02_PIN, BXT_GP_CAMERASB02_OFFSET},
+	{BXT_GP_CAMERASB03_PIN, BXT_GP_CAMERASB03_OFFSET},
+	{BXT_GP_CAMERASB04_PIN, BXT_GP_CAMERASB04_OFFSET},
+	{BXT_GP_CAMERASB05_PIN, BXT_GP_CAMERASB05_OFFSET},
+	{BXT_GP_CAMERASB06_PIN, BXT_GP_CAMERASB06_OFFSET},
+	{BXT_GP_CAMERASB07_PIN, BXT_GP_CAMERASB07_OFFSET},
+	{BXT_GP_CAMERASB08_PIN, BXT_GP_CAMERASB08_OFFSET},
+	{BXT_GP_CAMERASB09_PIN, BXT_GP_CAMERASB09_OFFSET},
+	{BXT_GP_CAMERASB10_PIN, BXT_GP_CAMERASB10_OFFSET},
+	{BXT_GP_CAMERASB11_PIN, BXT_GP_CAMERASB11_OFFSET},
+};
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
 	return port ? PORT_C : PORT_A;
@@ -796,6 +1426,53 @@  void chv_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 action)
 
 }
 
+void bxt_program_gpio(struct intel_dsi *intel_dsi, u8 gpio, u8 value)
+{
+	u16 gpio_number = 0, i;
+	int err;
+
+	for (i = 0; i < ARRAY_SIZE(bxt_gtable); i++) {
+		if (bxt_gtable[i].gpio_pin == gpio) {
+			gpio_number = bxt_gtable[i].offset;
+
+			if (!gpio_number) {
+				DRM_ERROR("Invalid GPIO requested\n");
+				return;
+			}
+			if (!bxt_gtable[i].pin_requested) {
+				err = gpio_request_one(gpio_number,
+						GPIOF_DIR_OUT, "MIPI");
+				if (err) {
+					DRM_ERROR("unable to get GPIO %d\n",
+							gpio_number);
+					return;
+				}
+				bxt_gtable[i].pin_requested = true;
+			}
+		}
+	}
+
+	if (!gpio_number) {
+		DRM_ERROR("Requested GPIO not found in the table\n");
+		return;
+	}
+
+	gpio_set_value(gpio_number, value);
+}
+
+void bxt_free_gpio(struct intel_dsi *intel_dsi)
+{
+	int i;
+	u16 gpio_number;
+
+	for (i = 0; i < ARRAY_SIZE(bxt_gtable); i++) {
+		if (bxt_gtable[i].pin_requested) {
+			gpio_number = bxt_gtable[i].offset;
+			gpio_free(gpio_number);
+		}
+	}
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	u8 gpio, action;
@@ -821,6 +1498,8 @@  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 		vlv_program_gpio(intel_dsi, gpio, action);
 	else if (IS_CHERRYVIEW(dev))
 		chv_program_gpio(intel_dsi, gpio, action);
+	else if (IS_BROXTON(dev))
+		bxt_program_gpio(intel_dsi, gpio, action);
 	else
 		DRM_ERROR("GPIO programming missing for this platform.\n");
 
@@ -991,6 +1670,14 @@  static const struct drm_panel_funcs vbt_panel_funcs = {
 	.get_modes = vbt_panel_get_modes,
 };
 
+void vbt_panel_exit(struct intel_dsi *intel_dsi)
+{
+	struct drm_device *dev = intel_dsi->base.base.dev;
+
+	if (IS_BROXTON(dev))
+		bxt_free_gpio(intel_dsi);
+}
+
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;