[2/5] drm/i915: Do not read GAMMA_MODE register

Submitted by Lionel Landwerlin on Feb. 25, 2016, 10:58 a.m.

Details

Message ID 1456397929-27406-3-git-send-email-lionel.g.landwerlin@intel.com
State New
Headers show
Series "Pipe level color management V8" ( rev: 1 ) in DRI devel

Not browsing as part of any series.

Commit Message

Lionel Landwerlin Feb. 25, 2016, 10:58 a.m.
Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.

v2: Read GAMMA_MODE register value at init (Matt Roper's comment)

v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
    with other registers (Matt Roper's comment).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   | 12 ++++++++----
 drivers/gpu/drm/i915/intel_display.c |  2 ++
 drivers/gpu/drm/i915/intel_drv.h     |  3 +++
 3 files changed, 13 insertions(+), 4 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5e0b997..16657eb 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -121,6 +121,8 @@  static void haswell_load_luts(struct drm_crtc *crtc)
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_crtc_state *intel_crtc_state =
+		to_intel_crtc_state(crtc->state);
 	bool reenable_ips = false;
 
 	/*
@@ -128,11 +130,12 @@  static void haswell_load_luts(struct drm_crtc *crtc)
 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 	 */
 	if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
-	    ((I915_READ(GAMMA_MODE(intel_crtc->pipe)) & GAMMA_MODE_MODE_MASK) ==
-	     GAMMA_MODE_MODE_SPLIT)) {
+	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
 		hsw_disable_ips(intel_crtc);
 		reenable_ips = true;
 	}
+
+	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
 
 	i9xx_load_luts(crtc);
@@ -183,8 +186,9 @@  void intel_color_init(struct drm_crtc *crtc)
 	}
 
 	if (IS_HASWELL(dev) ||
-	    (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)))
+	    (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev))) {
 		dev_priv->display.load_luts = haswell_load_luts;
-	else
+	} else {
 		dev_priv->display.load_luts = i9xx_load_luts;
+	}
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index acbb1d9..19f8284 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9891,6 +9891,8 @@  static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
 	intel_get_pipe_timings(crtc, pipe_config);
 
+	pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
+
 	if (INTEL_INFO(dev)->gen >= 9) {
 		skl_init_scalers(dev, crtc, pipe_config);
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7532f61..8c48131 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -517,6 +517,9 @@  struct intel_crtc_state {
 			struct skl_pipe_wm skl;
 		} optimal;
 	} wm;
+
+	/* Gamma mode programmed on the pipe */
+	uint32_t gamma_mode;
 };
 
 struct vlv_wm_state {

Comments

On Thu, Feb 25, 2016 at 10:58:46AM +0000, Lionel Landwerlin wrote:
> Implement Daniel Stone's recommendation to not read registers to infer
> the hardware's state.
> 
> v2: Read GAMMA_MODE register value at init (Matt Roper's comment)
> 
> v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
>     with other registers (Matt Roper's comment).
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_color.c   | 12 ++++++++----
>  drivers/gpu/drm/i915/intel_display.c |  2 ++
>  drivers/gpu/drm/i915/intel_drv.h     |  3 +++
>  3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5e0b997..16657eb 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -121,6 +121,8 @@ static void haswell_load_luts(struct drm_crtc *crtc)
>  	struct drm_device *dev = crtc->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct intel_crtc_state *intel_crtc_state =
> +		to_intel_crtc_state(crtc->state);
>  	bool reenable_ips = false;
>  
>  	/*
> @@ -128,11 +130,12 @@ static void haswell_load_luts(struct drm_crtc *crtc)
>  	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
>  	 */
>  	if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
> -	    ((I915_READ(GAMMA_MODE(intel_crtc->pipe)) & GAMMA_MODE_MODE_MASK) ==
> -	     GAMMA_MODE_MODE_SPLIT)) {
> +	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
>  		hsw_disable_ips(intel_crtc);
>  		reenable_ips = true;
>  	}
> +
> +	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>  	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
>  
>  	i9xx_load_luts(crtc);
> @@ -183,8 +186,9 @@ void intel_color_init(struct drm_crtc *crtc)
>  	}
>  
>  	if (IS_HASWELL(dev) ||
> -	    (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)))
> +	    (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev))) {
>  		dev_priv->display.load_luts = haswell_load_luts;
> -	else
> +	} else {
>  		dev_priv->display.load_luts = i9xx_load_luts;
> +	}
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index acbb1d9..19f8284 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9891,6 +9891,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
>  
>  	intel_get_pipe_timings(crtc, pipe_config);
>  
> +	pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));

I think you want to mask this with GAMMA_MODE_MODE_MASK since there may
be stuff in the higher bits.

With that change made, you can consider this patch

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> +
>  	if (INTEL_INFO(dev)->gen >= 9) {
>  		skl_init_scalers(dev, crtc, pipe_config);
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7532f61..8c48131 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -517,6 +517,9 @@ struct intel_crtc_state {
>  			struct skl_pipe_wm skl;
>  		} optimal;
>  	} wm;
> +
> +	/* Gamma mode programmed on the pipe */
> +	uint32_t gamma_mode;
>  };
>  
>  struct vlv_wm_state {
> -- 
> 2.7.0
> 
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