[1/2] drm/dp: Add definition for Display Control DPCD Registers capability size

Submitted by Yetunde Adebisi on Feb. 5, 2016, 12:18 p.m.

Details

Message ID 1454674733-7279-2-git-send-email-yetundex.adebisi@intel.com
State New
Headers show
Series "DPCD Backlight Control" ( rev: 3 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Yetunde Adebisi Feb. 5, 2016, 12:18 p.m.
This is used when reading Display Control capability Registers on the sink
device.

cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

Patch hide | download patch | download mbox

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@  u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
+#define EDP_DISPLAY_CTL_CAP_SIZE	3
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);