drm/i915/skl/kbl: Add support for pipe fusing

Submitted by Patrik Jakobsson on Jan. 18, 2016, 2:11 p.m.

Details

Message ID 1453126317-28674-1-git-send-email-patrik.jakobsson@linux.intel.com
State New
Headers show
Series "drm/i915/skl/kbl: Add support for pipe fusing" ( rev: 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Patrik Jakobsson Jan. 18, 2016, 2:11 p.m.
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
several registers that can contain fuse settings so to simplify things
we keep around a mask in device info with bits for each disabled pipe.
This will also come in handy if the rule about the descending order is
changed on future platforms.

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_reg.h |  4 ++++
 3 files changed, 39 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 988a380..2e9d47d 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -814,6 +814,40 @@  static void intel_device_info_runtime_init(struct drm_device *dev)
 			DRM_INFO("Display fused off, disabling\n");
 			info->num_pipes = 0;
 		}
+	} else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
+		u32 fuse_strap = I915_READ(FUSE_STRAP);
+		u32 dfsm = I915_READ(SKL_DFSM);
+		bool invalid;
+		int num_bits;
+
+		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
+			info->pipe_disabled_mask |= BIT(PIPE_A);
+		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
+			info->pipe_disabled_mask |= BIT(PIPE_B);
+		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
+			info->pipe_disabled_mask |= BIT(PIPE_C);
+
+		if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
+			info->pipe_disabled_mask |= BIT(PIPE_C);
+
+		num_bits = hweight8(info->pipe_disabled_mask);
+
+		switch (info->pipe_disabled_mask) {
+			case BIT(PIPE_A):
+			case BIT(PIPE_B):
+			case BIT(PIPE_A) | BIT(PIPE_B):
+			case BIT(PIPE_A) | BIT(PIPE_C):
+				invalid = true;
+				break;
+			default:
+				invalid = false;
+		}
+
+		if (num_bits > info->num_pipes || invalid)
+			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
+				  info->pipe_disabled_mask);
+		else
+			info->num_pipes -= num_bits;
 	}
 
 	/* Initialize slice/subslice/EU info */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f0f75d7..2b4783c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -792,6 +792,7 @@  struct intel_device_info {
 	u8 num_pipes:3;
 	u8 num_sprites[I915_MAX_PIPES];
 	u8 gen;
+	u8 pipe_disabled_mask;
 	u8 ring_mask; /* Rings supported by the HW */
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 	/* Register offsets for the various display pipes and transcoders */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7510d508..72f07e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5940,6 +5940,7 @@  enum skl_disp_power_wells {
 #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
 #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
 #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
+#define  SKL_DISPLAY_PIPE_C_DISABLE	(1 << 28)
 #define  ILK_HDCP_DISABLE		(1 << 25)
 #define  ILK_eDP_A_DISABLE		(1 << 24)
 #define  HSW_CDCLK_LIMIT		(1 << 24)
@@ -5986,6 +5987,9 @@  enum skl_disp_power_wells {
 #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
 #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
 
 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)

Comments

On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> several registers that can contain fuse settings so to simplify things
> we keep around a mask in device info with bits for each disabled pipe.
> This will also come in handy if the rule about the descending order is
> changed on future platforms.
> 
> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
>  3 files changed, 39 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 988a380..2e9d47d 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  			DRM_INFO("Display fused off, disabling\n");
>  			info->num_pipes = 0;
>  		}
> +	} else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> +		u32 fuse_strap = I915_READ(FUSE_STRAP);
> +		u32 dfsm = I915_READ(SKL_DFSM);
> +		bool invalid;
> +		int num_bits;
> +
> +		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> +			info->pipe_disabled_mask |= BIT(PIPE_A);
> +		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> +			info->pipe_disabled_mask |= BIT(PIPE_B);
> +		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> +			info->pipe_disabled_mask |= BIT(PIPE_C);
> +
> +		if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> +			info->pipe_disabled_mask |= BIT(PIPE_C);
> +
> +		num_bits = hweight8(info->pipe_disabled_mask);
> +
> +		switch (info->pipe_disabled_mask) {
> +			case BIT(PIPE_A):
> +			case BIT(PIPE_B):
> +			case BIT(PIPE_A) | BIT(PIPE_B):
> +			case BIT(PIPE_A) | BIT(PIPE_C):
> +				invalid = true;
> +				break;
> +			default:
> +				invalid = false;
> +		}
> +
> +		if (num_bits > info->num_pipes || invalid)
> +			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> +				  info->pipe_disabled_mask);
> +		else
> +			info->num_pipes -= num_bits;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f0f75d7..2b4783c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -792,6 +792,7 @@ struct intel_device_info {
>  	u8 num_pipes:3;
>  	u8 num_sprites[I915_MAX_PIPES];
>  	u8 gen;
> +	u8 pipe_disabled_mask;
>  	u8 ring_mask; /* Rings supported by the HW */
>  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
>  	/* Register offsets for the various display pipes and transcoders */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7510d508..72f07e6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
>  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
>  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
>  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
> +#define  SKL_DISPLAY_PIPE_C_DISABLE	(1 << 28)

Maybe you want to go review the other patch that wants to add this bit?

>  #define  ILK_HDCP_DISABLE		(1 << 25)
>  #define  ILK_eDP_A_DISABLE		(1 << 24)
>  #define  HSW_CDCLK_LIMIT		(1 << 24)
> @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
>  #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
>  #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> +#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> +#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> +#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>  
>  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> > several registers that can contain fuse settings so to simplify things
> > we keep around a mask in device info with bits for each disabled pipe.
> > This will also come in handy if the rule about the descending order is
> > changed on future platforms.
> > 
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> >  3 files changed, 39 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 988a380..2e9d47d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> >  			DRM_INFO("Display fused off, disabling\n");
> >  			info->num_pipes = 0;
> >  		}
> > +	} else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> > +		u32 fuse_strap = I915_READ(FUSE_STRAP);
> > +		u32 dfsm = I915_READ(SKL_DFSM);
> > +		bool invalid;
> > +		int num_bits;
> > +
> > +		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_A);
> > +		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_B);
> > +		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > +		if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > +		num_bits = hweight8(info->pipe_disabled_mask);
> > +
> > +		switch (info->pipe_disabled_mask) {
> > +			case BIT(PIPE_A):
> > +			case BIT(PIPE_B):
> > +			case BIT(PIPE_A) | BIT(PIPE_B):
> > +			case BIT(PIPE_A) | BIT(PIPE_C):
> > +				invalid = true;
> > +				break;
> > +			default:
> > +				invalid = false;
> > +		}
> > +
> > +		if (num_bits > info->num_pipes || invalid)
> > +			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> > +				  info->pipe_disabled_mask);
> > +		else
> > +			info->num_pipes -= num_bits;
> >  	}
> >  
> >  	/* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f0f75d7..2b4783c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -792,6 +792,7 @@ struct intel_device_info {
> >  	u8 num_pipes:3;
> >  	u8 num_sprites[I915_MAX_PIPES];
> >  	u8 gen;
> > +	u8 pipe_disabled_mask;
> >  	u8 ring_mask; /* Rings supported by the HW */
> >  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> >  	/* Register offsets for the various display pipes and transcoders */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7510d508..72f07e6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> >  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
> >  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> >  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
> > +#define  SKL_DISPLAY_PIPE_C_DISABLE	(1 << 28)
> 
> Maybe you want to go review the other patch that wants to add this bit?
> 

Thanks for the heads up, I hadn't seen that one from Gabriel. I'll let his patch
land first.

> >  #define  ILK_HDCP_DISABLE		(1 << 25)
> >  #define  ILK_eDP_A_DISABLE		(1 << 24)
> >  #define  HSW_CDCLK_LIMIT		(1 << 24)
> > @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> >  #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> > +#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> > +#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> > +#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> >  
> >  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
> >  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> > -- 
> > 2.5.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
On Mon, Jan 18, 2016 at 06:01:27PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 18, 2016 at 03:11:57PM +0100, Patrik Jakobsson wrote:
> > On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
> > pipes must be fused in descending order (e.g. C, B+C, A+B+C). There are
> > several registers that can contain fuse settings so to simplify things
> > we keep around a mask in device info with bits for each disabled pipe.
> > This will also come in handy if the rule about the descending order is
> > changed on future platforms.
> > 
> > Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_dma.c | 34 ++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/i915_reg.h |  4 ++++
> >  3 files changed, 39 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 988a380..2e9d47d 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -814,6 +814,40 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> >  			DRM_INFO("Display fused off, disabling\n");
> >  			info->num_pipes = 0;
> >  		}
> > +	} else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {
> > +		u32 fuse_strap = I915_READ(FUSE_STRAP);
> > +		u32 dfsm = I915_READ(SKL_DFSM);
> > +		bool invalid;
> > +		int num_bits;
> > +
> > +		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_A);
> > +		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_B);
> > +		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > +		if (fuse_strap & SKL_DISPLAY_PIPE_C_DISABLE)
> > +			info->pipe_disabled_mask |= BIT(PIPE_C);
> > +
> > +		num_bits = hweight8(info->pipe_disabled_mask);
> > +
> > +		switch (info->pipe_disabled_mask) {
> > +			case BIT(PIPE_A):
> > +			case BIT(PIPE_B):
> > +			case BIT(PIPE_A) | BIT(PIPE_B):
> > +			case BIT(PIPE_A) | BIT(PIPE_C):
> > +				invalid = true;
> > +				break;
> > +			default:
> > +				invalid = false;
> > +		}
> > +
> > +		if (num_bits > info->num_pipes || invalid)
> > +			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
> > +				  info->pipe_disabled_mask);
> > +		else
> > +			info->num_pipes -= num_bits;
> >  	}
> >  
> >  	/* Initialize slice/subslice/EU info */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f0f75d7..2b4783c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -792,6 +792,7 @@ struct intel_device_info {
> >  	u8 num_pipes:3;
> >  	u8 num_sprites[I915_MAX_PIPES];
> >  	u8 gen;
> > +	u8 pipe_disabled_mask;
> >  	u8 ring_mask; /* Rings supported by the HW */
> >  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> >  	/* Register offsets for the various display pipes and transcoders */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7510d508..72f07e6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5940,6 +5940,7 @@ enum skl_disp_power_wells {
> >  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
> >  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
> >  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
> > +#define  SKL_DISPLAY_PIPE_C_DISABLE	(1 << 28)
> 
> Maybe you want to go review the other patch that wants to add this bit?
> 

My bad, we shouldn't look at FUSE_STRAP on SKL+. I'll resend without it.

> >  #define  ILK_HDCP_DISABLE		(1 << 25)
> >  #define  ILK_eDP_A_DISABLE		(1 << 24)
> >  #define  HSW_CDCLK_LIMIT		(1 << 24)
> > @@ -5986,6 +5987,9 @@ enum skl_disp_power_wells {
> >  #define SKL_DFSM_CDCLK_LIMIT_540	(1 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_450	(2 << 23)
> >  #define SKL_DFSM_CDCLK_LIMIT_337_5	(3 << 23)
> > +#define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> > +#define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> > +#define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
> >  
> >  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
> >  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> > -- 
> > 2.5.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC