[08/10] drm/i915: Refactor LPT-H VGA dotclock disabling

Submitted by Ville Syrjälä on Dec. 1, 2015, 1:08 p.m.

Details

Message ID 1448975321-20192-9-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show
Series "HSW/BDW PCH modeset fixes and stuff" ( rev: 9 8 7 6 4 3 2 5 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Ville Syrjälä Dec. 1, 2015, 1:08 p.m.
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract the LPT-H VGA dotclock disable to a separate function in
anticipation of further use.

While at it move the sb_lock locking inwards when enabling the VGA
dotclock, as it's only needed to protect the sideband accesses.

Also toss out the PIXCLK_GATE_GATE nop define and just use 0.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  1 -
 drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++--------------
 2 files changed, 20 insertions(+), 15 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fcc819f400a6..3a9819735833 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7342,7 +7342,6 @@  enum skl_disp_power_wells {
 /* LPT PIXCLK_GATE */
 #define PIXCLK_GATE			_MMIO(0xC6020)
 #define  PIXCLK_GATE_UNGATE		(1<<0)
-#define  PIXCLK_GATE_GATE		(0<<0)
 
 /* SPLL */
 #define SPLL_CTL			_MMIO(0x46020)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1dc125b6dcdc..322a35c67870 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3938,6 +3938,21 @@  static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
 	return 0;
 }
 
+static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
+{
+	u32 temp;
+
+	I915_WRITE(PIXCLK_GATE, 0);
+
+	mutex_lock(&dev_priv->sb_lock);
+
+	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
+	temp |= SBI_SSCCTL_DISABLE;
+	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
+
+	mutex_unlock(&dev_priv->sb_lock);
+}
+
 /* Program iCLKIP clock to the desired frequency */
 static void lpt_program_iclkip(struct drm_crtc *crtc)
 {
@@ -3947,18 +3962,7 @@  static void lpt_program_iclkip(struct drm_crtc *crtc)
 	u32 divsel, phaseinc, auxdiv, phasedir = 0;
 	u32 temp;
 
-	mutex_lock(&dev_priv->sb_lock);
-
-	/* It is necessary to ungate the pixclk gate prior to programming
-	 * the divisors, and gate it back when it is done.
-	 */
-	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
-
-	/* Disable SSCCTL */
-	intel_sbi_write(dev_priv, SBI_SSCCTL6,
-			intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
-				SBI_SSCCTL_DISABLE,
-			SBI_ICLK);
+	lpt_disable_iclkip(dev_priv);
 
 	/* 20MHz is a corner case which is out of range for the 7-bit divisor */
 	if (clock == 20000) {
@@ -3998,6 +4002,8 @@  static void lpt_program_iclkip(struct drm_crtc *crtc)
 			phasedir,
 			phaseinc);
 
+	mutex_lock(&dev_priv->sb_lock);
+
 	/* Program SSCDIVINTPHASE6 */
 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
 	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
@@ -4019,12 +4025,12 @@  static void lpt_program_iclkip(struct drm_crtc *crtc)
 	temp &= ~SBI_SSCCTL_DISABLE;
 	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
 
+	mutex_unlock(&dev_priv->sb_lock);
+
 	/* Wait for initialization time */
 	udelay(24);
 
 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
-
-	mutex_unlock(&dev_priv->sb_lock);
 }
 
 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,

Comments

2015-12-01 11:08 GMT-02:00  <ville.syrjala@linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the LPT-H VGA dotclock disable to a separate function in
> anticipation of further use.
>
> While at it move the sb_lock locking inwards when enabling the VGA
> dotclock, as it's only needed to protect the sideband accesses.
>
> Also toss out the PIXCLK_GATE_GATE nop define and just use 0.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  1 -
>  drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++--------------
>  2 files changed, 20 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fcc819f400a6..3a9819735833 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7342,7 +7342,6 @@ enum skl_disp_power_wells {
>  /* LPT PIXCLK_GATE */
>  #define PIXCLK_GATE                    _MMIO(0xC6020)
>  #define  PIXCLK_GATE_UNGATE            (1<<0)
> -#define  PIXCLK_GATE_GATE              (0<<0)

I actually liked the #define...

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

>
>  /* SPLL */
>  #define SPLL_CTL                       _MMIO(0x46020)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1dc125b6dcdc..322a35c67870 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3938,6 +3938,21 @@ static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
>         return 0;
>  }
>
> +static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
> +{
> +       u32 temp;
> +
> +       I915_WRITE(PIXCLK_GATE, 0);
> +
> +       mutex_lock(&dev_priv->sb_lock);
> +
> +       temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> +       temp |= SBI_SSCCTL_DISABLE;
> +       intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> +
> +       mutex_unlock(&dev_priv->sb_lock);
> +}
> +
>  /* Program iCLKIP clock to the desired frequency */
>  static void lpt_program_iclkip(struct drm_crtc *crtc)
>  {
> @@ -3947,18 +3962,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
>         u32 divsel, phaseinc, auxdiv, phasedir = 0;
>         u32 temp;
>
> -       mutex_lock(&dev_priv->sb_lock);
> -
> -       /* It is necessary to ungate the pixclk gate prior to programming
> -        * the divisors, and gate it back when it is done.
> -        */
> -       I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
> -
> -       /* Disable SSCCTL */
> -       intel_sbi_write(dev_priv, SBI_SSCCTL6,
> -                       intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
> -                               SBI_SSCCTL_DISABLE,
> -                       SBI_ICLK);
> +       lpt_disable_iclkip(dev_priv);
>
>         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
>         if (clock == 20000) {
> @@ -3998,6 +4002,8 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
>                         phasedir,
>                         phaseinc);
>
> +       mutex_lock(&dev_priv->sb_lock);
> +
>         /* Program SSCDIVINTPHASE6 */
>         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
>         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> @@ -4019,12 +4025,12 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
>         temp &= ~SBI_SSCCTL_DISABLE;
>         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
>
> +       mutex_unlock(&dev_priv->sb_lock);
> +
>         /* Wait for initialization time */
>         udelay(24);
>
>         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
> -
> -       mutex_unlock(&dev_priv->sb_lock);
>  }
>
>  static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Dec 02, 2015 at 02:56:01PM -0200, Paulo Zanoni wrote:
> 2015-12-01 11:08 GMT-02:00  <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Extract the LPT-H VGA dotclock disable to a separate function in
> > anticipation of further use.
> >
> > While at it move the sb_lock locking inwards when enabling the VGA
> > dotclock, as it's only needed to protect the sideband accesses.
> >
> > Also toss out the PIXCLK_GATE_GATE nop define and just use 0.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  1 -
> >  drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++--------------
> >  2 files changed, 20 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index fcc819f400a6..3a9819735833 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7342,7 +7342,6 @@ enum skl_disp_power_wells {
> >  /* LPT PIXCLK_GATE */
> >  #define PIXCLK_GATE                    _MMIO(0xC6020)
> >  #define  PIXCLK_GATE_UNGATE            (1<<0)
> > -#define  PIXCLK_GATE_GATE              (0<<0)
> 
> I actually liked the #define...

I can keep it if you prefer. Just personally not too fond of defines for
zeroes.

> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> >
> >  /* SPLL */
> >  #define SPLL_CTL                       _MMIO(0x46020)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 1dc125b6dcdc..322a35c67870 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3938,6 +3938,21 @@ static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
> >         return 0;
> >  }
> >
> > +static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
> > +{
> > +       u32 temp;
> > +
> > +       I915_WRITE(PIXCLK_GATE, 0);
> > +
> > +       mutex_lock(&dev_priv->sb_lock);
> > +
> > +       temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> > +       temp |= SBI_SSCCTL_DISABLE;
> > +       intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> > +
> > +       mutex_unlock(&dev_priv->sb_lock);
> > +}
> > +
> >  /* Program iCLKIP clock to the desired frequency */
> >  static void lpt_program_iclkip(struct drm_crtc *crtc)
> >  {
> > @@ -3947,18 +3962,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
> >         u32 divsel, phaseinc, auxdiv, phasedir = 0;
> >         u32 temp;
> >
> > -       mutex_lock(&dev_priv->sb_lock);
> > -
> > -       /* It is necessary to ungate the pixclk gate prior to programming
> > -        * the divisors, and gate it back when it is done.
> > -        */
> > -       I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
> > -
> > -       /* Disable SSCCTL */
> > -       intel_sbi_write(dev_priv, SBI_SSCCTL6,
> > -                       intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
> > -                               SBI_SSCCTL_DISABLE,
> > -                       SBI_ICLK);
> > +       lpt_disable_iclkip(dev_priv);
> >
> >         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
> >         if (clock == 20000) {
> > @@ -3998,6 +4002,8 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
> >                         phasedir,
> >                         phaseinc);
> >
> > +       mutex_lock(&dev_priv->sb_lock);
> > +
> >         /* Program SSCDIVINTPHASE6 */
> >         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
> >         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> > @@ -4019,12 +4025,12 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
> >         temp &= ~SBI_SSCCTL_DISABLE;
> >         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
> >
> > +       mutex_unlock(&dev_priv->sb_lock);
> > +
> >         /* Wait for initialization time */
> >         udelay(24);
> >
> >         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
> > -
> > -       mutex_unlock(&dev_priv->sb_lock);
> >  }
> >
> >  static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
> > --
> > 2.4.10
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni