[12/15] drm/i915: Reduce seqno/irq barrier to a clflush on legacy gen6+

Submitted by Chris Wilson on Nov. 29, 2015, 8:48 a.m.

Details

Message ID 1448786893-2522-13-git-send-email-chris@chris-wilson.co.uk
State New
Headers show
Series "Series without cover letter" ( rev: 8 7 6 5 4 3 2 1 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Chris Wilson Nov. 29, 2015, 8:48 a.m.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3d59dd555e64..ccceb43f14ac 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1501,11 +1501,7 @@  pc_render_add_request(struct drm_i915_gem_request *req)
 static void
 gen6_seqno_barrier(struct intel_engine_cs *ring)
 {
-	/* Workaround to force correct ordering between irq and seqno writes on
-	 * ivb (and maybe also on snb) by reading from a CS register (like
-	 * ACTHD) before reading the status page. */
-	struct drm_i915_private *dev_priv = ring->i915;
-	POSTING_READ(RING_ACTHD(ring->mmio_base));
+	intel_flush_status_page(ring, I915_GEM_HWS_INDEX);
 }
 
 static bool