[Mesa-dev] gallium/radeon: add a debug flag not to use write combining

Submitted by Marek Olšák on Aug. 3, 2015, 12:36 p.m.

Details

Message ID 1438605377-2620-1-git-send-email-maraeo@gmail.com
State New
Headers show

Not browsing as part of any series.

Commit Message

Marek Olšák Aug. 3, 2015, 12:36 p.m.
From: Marek Olšák <marek.olsak@amd.com>

---
 src/gallium/drivers/radeon/r600_buffer_common.c | 6 ++++--
 src/gallium/drivers/radeon/r600_pipe_common.c   | 1 +
 src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
 3 files changed, 6 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index fc5f6c2..d5ee188 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -111,7 +111,8 @@  bool r600_init_resource(struct r600_common_screen *rscreen,
 
 	switch (res->b.b.usage) {
 	case PIPE_USAGE_STREAM:
-		flags = RADEON_FLAG_GTT_WC;
+		if (!(rscreen->debug_flags & DBG_NO_WC))
+			flags = RADEON_FLAG_GTT_WC;
 		/* fall through */
 	case PIPE_USAGE_STAGING:
 		/* Transfers are likely to occur more often with these resources. */
@@ -133,7 +134,8 @@  bool r600_init_resource(struct r600_common_screen *rscreen,
 	default:
 		/* Not listing GTT here improves performance in some apps. */
 		res->domains = RADEON_DOMAIN_VRAM;
-		flags |= RADEON_FLAG_GTT_WC;
+		if (!(rscreen->debug_flags & DBG_NO_WC))
+			flags |= RADEON_FLAG_GTT_WC;
 		break;
 	}
 
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 79b4b54..b12992d 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -351,6 +351,7 @@  static const struct debug_named_value common_debug_options[] = {
 	{ "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
 	{ "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
 	{ "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
+	{ "nowc", DBG_NO_WC, "Disable GTT write combining" },
 
 	DEBUG_NAMED_VALUE_END /* must be last */
 };
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index fbd2a21..01c4bd3 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -95,6 +95,7 @@ 
 #define DBG_FORCE_DMA		(1llu << 38)
 #define DBG_PRECOMPILE		(1llu << 39)
 #define DBG_INFO		(1llu << 40)
+#define DBG_NO_WC		(1llu << 41)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 

Comments

On 03.08.2015 21:36, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak@amd.com>
> 
> ---
>  src/gallium/drivers/radeon/r600_buffer_common.c | 6 ++++--
>  src/gallium/drivers/radeon/r600_pipe_common.c   | 1 +
>  src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
>  3 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
> index fc5f6c2..d5ee188 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -111,7 +111,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>  
>  	switch (res->b.b.usage) {
>  	case PIPE_USAGE_STREAM:
> -		flags = RADEON_FLAG_GTT_WC;
> +		if (!(rscreen->debug_flags & DBG_NO_WC))
> +			flags = RADEON_FLAG_GTT_WC;
>  		/* fall through */
>  	case PIPE_USAGE_STAGING:
>  		/* Transfers are likely to occur more often with these resources. */
> @@ -133,7 +134,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>  	default:
>  		/* Not listing GTT here improves performance in some apps. */
>  		res->domains = RADEON_DOMAIN_VRAM;
> -		flags |= RADEON_FLAG_GTT_WC;
> +		if (!(rscreen->debug_flags & DBG_NO_WC))
> +			flags |= RADEON_FLAG_GTT_WC;
>  		break;
>  	}

I think it would be both simpler and safer to mask out
RADEON_FLAG_GTT_WC after all the code which sets the various flags.
On a related note, can we disable HDP flushes and other flushes for
USWC when we don't use write
combining and CPU writes to VRAM? Maybe by adding a per-IB flag that
would instruct the
kernel to flush or not flush HDP?

Marek

On Wed, Aug 5, 2015 at 4:18 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On 03.08.2015 21:36, Marek Olšák wrote:
>> From: Marek Olšák <marek.olsak@amd.com>
>>
>> ---
>>  src/gallium/drivers/radeon/r600_buffer_common.c | 6 ++++--
>>  src/gallium/drivers/radeon/r600_pipe_common.c   | 1 +
>>  src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
>>  3 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
>> index fc5f6c2..d5ee188 100644
>> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
>> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
>> @@ -111,7 +111,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>>
>>       switch (res->b.b.usage) {
>>       case PIPE_USAGE_STREAM:
>> -             flags = RADEON_FLAG_GTT_WC;
>> +             if (!(rscreen->debug_flags & DBG_NO_WC))
>> +                     flags = RADEON_FLAG_GTT_WC;
>>               /* fall through */
>>       case PIPE_USAGE_STAGING:
>>               /* Transfers are likely to occur more often with these resources. */
>> @@ -133,7 +134,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>>       default:
>>               /* Not listing GTT here improves performance in some apps. */
>>               res->domains = RADEON_DOMAIN_VRAM;
>> -             flags |= RADEON_FLAG_GTT_WC;
>> +             if (!(rscreen->debug_flags & DBG_NO_WC))
>> +                     flags |= RADEON_FLAG_GTT_WC;
>>               break;
>>       }
>
> I think it would be both simpler and safer to mask out
> RADEON_FLAG_GTT_WC after all the code which sets the various flags.
>
>
> --
> Earthling Michel Dänzer               |               http://www.amd.com
> Libre software enthusiast             |             Mesa and X developer
> can we disable HDP flushes and other flushes for
> USWC when we don't use write
> combining and CPU writes to VRAM?
Nope, write combining happens in the CPU before the write request is 
send over the PCIe bus.

The HDP is a (rather small) read/write cache in GPUs memory controller 
as far as I know.

Regards,
Christian.

On 06.08.2015 17:09, Marek Olšák wrote:
> On a related note, can we disable HDP flushes and other flushes for
> USWC when we don't use write
> combining and CPU writes to VRAM? Maybe by adding a per-IB flag that
> would instruct the
> kernel to flush or not flush HDP?
>
> Marek
>
> On Wed, Aug 5, 2015 at 4:18 AM, Michel Dänzer <michel@daenzer.net> wrote:
>> On 03.08.2015 21:36, Marek Olšák wrote:
>>> From: Marek Olšák <marek.olsak@amd.com>
>>>
>>> ---
>>>   src/gallium/drivers/radeon/r600_buffer_common.c | 6 ++++--
>>>   src/gallium/drivers/radeon/r600_pipe_common.c   | 1 +
>>>   src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
>>>   3 files changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
>>> index fc5f6c2..d5ee188 100644
>>> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
>>> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
>>> @@ -111,7 +111,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>>>
>>>        switch (res->b.b.usage) {
>>>        case PIPE_USAGE_STREAM:
>>> -             flags = RADEON_FLAG_GTT_WC;
>>> +             if (!(rscreen->debug_flags & DBG_NO_WC))
>>> +                     flags = RADEON_FLAG_GTT_WC;
>>>                /* fall through */
>>>        case PIPE_USAGE_STAGING:
>>>                /* Transfers are likely to occur more often with these resources. */
>>> @@ -133,7 +134,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>>>        default:
>>>                /* Not listing GTT here improves performance in some apps. */
>>>                res->domains = RADEON_DOMAIN_VRAM;
>>> -             flags |= RADEON_FLAG_GTT_WC;
>>> +             if (!(rscreen->debug_flags & DBG_NO_WC))
>>> +                     flags |= RADEON_FLAG_GTT_WC;
>>>                break;
>>>        }
>> I think it would be both simpler and safer to mask out
>> RADEON_FLAG_GTT_WC after all the code which sets the various flags.
>>
>>
>> --
>> Earthling Michel Dänzer               |               http://www.amd.com
>> Libre software enthusiast             |             Mesa and X developer
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On 07.08.2015 00:17, Christian König wrote:
>> can we disable HDP flushes and other flushes for USWC

What other flushes are you thinking of? If you mean the mb() in the
kernel which flushes the write-combining buffers, that's also needed for
the register writes regardless of write-combining.


>> when we don't use write combining and CPU writes to VRAM?
> Nope, write combining happens in the CPU before the write request is
> send over the PCIe bus.
> 
> The HDP is a (rather small) read/write cache in GPUs memory controller
> as far as I know.

Yes, that's my understanding as well.

In theory it might be possible to track if there have been any CPU
writes to VRAM since the last HDP flush, but it might be a lot of effort
for uncertain gain.