drm/i915: Postpone plane readout until after encoder readout

Submitted by Patrik Jakobsson on July 31, 2015, 1:04 p.m.

Details

Message ID 1438347848-11293-1-git-send-email-patrik.jakobsson@linux.intel.com
State New
Headers show

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Commit Message

Patrik Jakobsson July 31, 2015, 1:04 p.m.
When reading out hw state for planes we disable inactive planes which in
turn triggers an update of the watermarks. The update depends on the
crtc_clock being set which is done when reading out encoders. Thus
postpone the plane readout until after encoder readout.

This prevents a warning in skl_compute_linetime_wm() where pixel_rate
becomes 0 when crtc_clock is 0.

Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 38 +++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 16 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 13a6608..73b2d4a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15205,27 +15205,25 @@  static bool primary_get_hw_state(struct intel_crtc *crtc)
 	return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
 }
 
-static void readout_plane_state(struct intel_crtc *crtc,
-				struct intel_crtc_state *crtc_state)
+static void intel_sanitize_plane(struct intel_plane *plane)
 {
-	struct intel_plane *p;
 	struct intel_plane_state *plane_state;
-	bool active = crtc_state->base.active;
+	struct intel_crtc *crtc;
 
-	for_each_intel_plane(crtc->base.dev, p) {
-		if (crtc->pipe != p->pipe)
-			continue;
+	plane_state = to_intel_plane_state(plane->base.state);
 
-		plane_state = to_intel_plane_state(p->base.state);
+	if (!plane_state->base.crtc)
+		return;
 
-		if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
-			plane_state->visible = primary_get_hw_state(crtc);
-		else {
-			if (active)
-				p->disable_plane(&p->base, &crtc->base);
+	crtc = to_intel_crtc(plane_state->base.crtc);
 
-			plane_state->visible = false;
-		}
+	if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) {
+		plane_state->visible = primary_get_hw_state(crtc);
+	} else {
+		if (crtc->base.state->active)
+			plane->disable_plane(&plane->base, &crtc->base);
+
+		plane_state->visible = false;
 	}
 }
 
@@ -15276,7 +15274,6 @@  static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		}
 
 		crtc->base.hwmode = crtc->config->base.adjusted_mode;
-		readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
 
 		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
 			      crtc->base.base.id,
@@ -15349,6 +15346,7 @@  intel_modeset_setup_hw_state(struct drm_device *dev)
 	enum pipe pipe;
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
+	struct intel_plane *plane;
 	int i;
 
 	intel_modeset_readout_hw_state(dev);
@@ -15360,6 +15358,14 @@  intel_modeset_setup_hw_state(struct drm_device *dev)
 
 	for_each_pipe(dev_priv, pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+
+		for_each_intel_plane(crtc->base.dev, plane) {
+			if (crtc->pipe != plane->pipe)
+				continue;
+
+			intel_sanitize_plane(plane);
+		}
+
 		intel_sanitize_crtc(crtc);
 		intel_dump_pipe_config(crtc, crtc->config,
 				       "[setup_hw_state]");

Comments

Op 31-07-15 om 15:04 schreef Patrik Jakobsson:
> When reading out hw state for planes we disable inactive planes which in
> turn triggers an update of the watermarks. The update depends on the
> crtc_clock being set which is done when reading out encoders. Thus
> postpone the plane readout until after encoder readout.
>
> This prevents a warning in skl_compute_linetime_wm() where pixel_rate
> becomes 0 when crtc_clock is 0.
>
The plane loop doesn't have to be nested.

But that's just a minor nitpick, feel free to ignore..

Reviewed-By: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6911
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                 -1              302/302              301/302
SNB                                  315/315              315/315
IVB                                  336/336              336/336
BYT                 -2              283/283              281/283
HSW                                  378/378              378/378
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt@kms_flip@flip-vs-dpms-interruptible      PASS(1)      DMESG_WARN(1)
*BYT  igt@gem_partial_pwrite_pread@reads-uncached      PASS(1)      FAIL(1)
*BYT  igt@gem_tiled_partial_pwrite_pread@reads      PASS(1)      FAIL(1)
Note: You need to pay more attention to line start with '*'