[09/16] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

Submitted by Michel Thierry on May 26, 2015, 2:21 p.m.

Details

Message ID 1432650084-24491-10-git-send-email-michel.thierry@intel.com
State New
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Commit Message

Michel Thierry May 26, 2015, 2:21 p.m.
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.

Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.

This patch was inspired by Ben's "Depend exclusively on map and
unmap_vma".

v2: Rebase after s/page_tables/page_table/.
v3: Remove unnecessary pdpe loop in gen8_ppgtt_clear_range_4lvl and use
clamp_pdp in gen8_ppgtt_insert_entries (Akash).
v4: Merge gen8_ppgtt_clear_range_4lvl into gen8_ppgtt_clear_range to
maintain symmetry with gen8_ppgtt_insert_entries (Akash).
v5: Do not mix pages and bytes in insert_entries (Akash).

Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 51 +++++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++++++++
 2 files changed, 54 insertions(+), 8 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2b6ee8e..dbbf367 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -651,18 +651,33 @@  static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 {
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
-	struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
-
 	gen8_pte_t scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 						 I915_CACHE_LLC, use_scratch);
 
-	gen8_ppgtt_clear_pte_range(pdp, start, length, scratch_pte, !HAS_LLC(vm->dev));
+	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
+		gen8_ppgtt_clear_pte_range(&ppgtt->pdp, start, length,
+					   scratch_pte,
+					   !HAS_LLC(ppgtt->base.dev));
+	} else {
+		uint64_t templ4, pml4e;
+		struct i915_page_directory_pointer *pdp;
+
+		gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
+			uint64_t pdp_len = gen8_clamp_pdp(start, length);
+			uint64_t pdp_start = start;
+
+			gen8_ppgtt_clear_pte_range(pdp, pdp_start, pdp_len,
+						   scratch_pte,
+						   !HAS_LLC(ppgtt->base.dev));
+		}
+	}
 }
 
 static void
 gen8_ppgtt_insert_pte_entries(struct i915_page_directory_pointer *pdp,
 			      struct sg_page_iter *sg_iter,
 			      uint64_t start,
+			      size_t pages,
 			      enum i915_cache_level cache_level,
 			      const bool flush)
 {
@@ -673,7 +688,7 @@  gen8_ppgtt_insert_pte_entries(struct i915_page_directory_pointer *pdp,
 
 	pt_vaddr = NULL;
 
-	while (__sg_page_iter_next(sg_iter)) {
+	while (pages-- && __sg_page_iter_next(sg_iter)) {
 		if (pt_vaddr == NULL) {
 			struct i915_page_directory *pd = pdp->page_directory[pdpe];
 			struct i915_page_table *pt = pd->page_table[pde];
@@ -710,12 +725,31 @@  static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 				      enum i915_cache_level cache_level,
 				      u32 unused)
 {
-	struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
-	struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
+	struct i915_hw_ppgtt *ppgtt =
+			container_of(vm, struct i915_hw_ppgtt, base);
 	struct sg_page_iter sg_iter;
 
 	__sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
-	gen8_ppgtt_insert_pte_entries(pdp, &sg_iter, start, cache_level, !HAS_LLC(vm->dev));
+
+	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
+		gen8_ppgtt_insert_pte_entries(&ppgtt->pdp, &sg_iter, start,
+					      sg_nents(pages->sgl),
+					      cache_level, !HAS_LLC(vm->dev));
+	} else {
+		struct i915_page_directory_pointer *pdp;
+		uint64_t templ4, pml4e;
+		uint64_t length = sg_nents(pages->sgl) << PAGE_SHIFT;
+
+		gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
+			uint64_t pdp_len = gen8_clamp_pdp(start, length) >> PAGE_SHIFT;
+			uint64_t pdp_start = start;
+
+			gen8_ppgtt_insert_pte_entries(pdp, &sg_iter,
+						      pdp_start, pdp_len,
+						      cache_level,
+						      !HAS_LLC(vm->dev));
+		}
+	}
 }
 
 static void __gen8_do_map_pt(gen8_pde_t * const pde,
@@ -1135,7 +1169,8 @@  static int __gen8_alloc_vma_range_3lvl(struct i915_address_space *vm,
 			if (sg_iter) {
 				WARN_ON(!sg_iter->__nents);
 				gen8_ppgtt_insert_pte_entries(pdp, sg_iter, pd_start,
-							      flags, !HAS_LLC(vm->dev));
+						gen8_pte_count(pd_start, pd_len),
+						flags, !HAS_LLC(vm->dev));
 			}
 			set_bit(pde, pd->used_pdes);
 		}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 9d53b64..9af33b2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -469,6 +469,17 @@  static inline uint32_t gen6_pde_index(uint32_t addr)
 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter)		\
 	gen8_for_each_pdpe_e(pd, pdp, start, length, temp, iter, I915_PDPES_PER_PDP(dev))
 
+/* Clamp length to the next page_directory pointer boundary */
+static inline uint64_t gen8_clamp_pdp(uint64_t start, uint64_t length)
+{
+	uint64_t next_pdp = ALIGN(start + 1, 1ULL << GEN8_PML4E_SHIFT);
+
+	if (next_pdp > (start + length))
+		return length;
+
+	return next_pdp - start;
+}
+
 static inline uint32_t gen8_pte_index(uint64_t address)
 {
 	return i915_pte_index(address, GEN8_PDE_SHIFT);

Comments

On 5/26/2015 3:21 PM, Michel Thierry wrote:
> When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
> Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
> it will write to.
>
> Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
>
> This patch was inspired by Ben's "Depend exclusively on map and
> unmap_vma".
>
> v2: Rebase after s/page_tables/page_table/.
> v3: Remove unnecessary pdpe loop in gen8_ppgtt_clear_range_4lvl and use
> clamp_pdp in gen8_ppgtt_insert_entries (Akash).
> v4: Merge gen8_ppgtt_clear_range_4lvl into gen8_ppgtt_clear_range to
> maintain symmetry with gen8_ppgtt_insert_entries (Akash).
> v5: Do not mix pages and bytes in insert_entries (Akash).
>
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 51 +++++++++++++++++++++++++++++++------
>   drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++++++++
>   2 files changed, 54 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 2b6ee8e..dbbf367 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -710,12 +725,31 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
>                                        enum i915_cache_level cache_level,
>                                        u32 unused)
>   {
> -       struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
> -       struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
> +       struct i915_hw_ppgtt *ppgtt =
> +                       container_of(vm, struct i915_hw_ppgtt, base);
>          struct sg_page_iter sg_iter;
>
>          __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
> -       gen8_ppgtt_insert_pte_entries(pdp, &sg_iter, start, cache_level, !HAS_LLC(vm->dev));
> +
> +       if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
> +               gen8_ppgtt_insert_pte_entries(&ppgtt->pdp, &sg_iter, start,
> +                                             sg_nents(pages->sgl),
> +                                             cache_level, !HAS_LLC(vm->dev));
> +       } else {
> +               struct i915_page_directory_pointer *pdp;
> +               uint64_t templ4, pml4e;
> +               uint64_t length = sg_nents(pages->sgl) << PAGE_SHIFT;

Actually, this should be:

	uint64_t length = (uint64_t)sg_nents(pages->sgl) << PAGE_SHIFT;

Otherwise it will overflow if we're inserting 4GB at once.

> +
> +               gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
> +                       uint64_t pdp_len = gen8_clamp_pdp(start, length) >> PAGE_SHIFT;
> +                       uint64_t pdp_start = start;
> +
> +                       gen8_ppgtt_insert_pte_entries(pdp, &sg_iter,
> +                                                     pdp_start, pdp_len,
> +                                                     cache_level,
> +                                                     !HAS_LLC(vm->dev));
> +               }
> +       }
>   }
>
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