[v2] drm/i915: Workaround to avoid lite restore with HEAD==TAIL

Submitted by Michel Thierry on April 14, 2015, 3:41 p.m.

Details

Message ID 1429026084-26800-1-git-send-email-michel.thierry@intel.com
State New
Headers show

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Commit Message

Michel Thierry April 14, 2015, 3:41 p.m.
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.

Add two extra MI_NOOP instructions at the end of each request, but keep
the requests tail pointing before the MI_NOOPs. We may not need to
executed them, and this is why request->tail must be sampled before adding
these extra instructions.

If we submit a context to the ELSP which has previously been submitted,
move the tail pointer past the MI_NOOPs. This ensures HEAD!=TAIL.

v2: Move overallocation to gen8_emit_request, and added note about
sampling request->tail in commit message (Chris).

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c  | 15 ++++++++++++++-
 drivers/gpu/drm/i915/intel_lrc.c | 27 ++++++++++++++++++++++++++-
 2 files changed, 40 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6dd0d57..dc94984 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2364,14 +2364,27 @@  int __i915_add_request(struct intel_engine_cs *ring,
 		ret = ring->emit_request(ringbuf, request);
 		if (ret)
 			return ret;
+
+		request->tail = intel_ring_get_tail(ringbuf);
+
+		if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
+			/*
+			 * Here we add two extra NOOPs as padding to avoid
+			 * lite restore of a context with HEAD==TAIL.
+			 */
+			intel_logical_ring_emit(ringbuf, MI_NOOP);
+			intel_logical_ring_emit(ringbuf, MI_NOOP);
+			intel_logical_ring_advance(ringbuf);
+		}
 	} else {
 		ret = ring->add_request(ring);
 		if (ret)
 			return ret;
+
+		request->tail = intel_ring_get_tail(ringbuf);
 	}
 
 	request->head = request_start;
-	request->tail = intel_ring_get_tail(ringbuf);
 
 	/* Whilst this request exists, batch_obj will be on the
 	 * active_list, and so will hold the active reference. Only when this
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2747b02..1614425 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -427,6 +427,26 @@  static void execlists_context_unqueue(struct intel_engine_cs *ring)
 		}
 	}
 
+	if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
+		/*
+		 * WaIdleLiteRestore: make sure we never cause a lite
+		 * restore with HEAD==TAIL
+		 */
+		if (req0 && req0->elsp_submitted == 1) {
+			/*
+			 * Consume the buffer NOOPs to ensure HEAD != TAIL when
+			 * submitting. elsp_submitted can only be >1 after
+			 * reset, in which case we don't need the workaround as
+			 * a lite restore will not occur.
+			 */
+			struct intel_ringbuffer *ringbuf;
+
+			ringbuf = req0->ctx->engine[ring->id].ringbuf;
+			req0->tail += 8;
+			req0->tail &= ringbuf->size - 1;
+		}
+	}
+
 	WARN_ON(req1 && req1->elsp_submitted);
 
 	execlists_submit_contexts(ring, req0->ctx, req0->tail,
@@ -1272,7 +1292,12 @@  static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
 	u32 cmd;
 	int ret;
 
-	ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
+	/*
+	 * Reserve space for 2 NOOPs at the end of each request to be
+	 * used as a workaround for not being allowed to do lite
+	 * restore with HEAD==TAIL.
+	 */
+	ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
 	if (ret)
 		return ret;
 

Comments

On Tue, Apr 14, 2015 at 04:41:24PM +0100, Michel Thierry wrote:
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6dd0d57..dc94984 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2364,14 +2364,27 @@ int __i915_add_request(struct intel_engine_cs *ring,
>  		ret = ring->emit_request(ringbuf, request);
>  		if (ret)
>  			return ret;
> +
> +		request->tail = intel_ring_get_tail(ringbuf);
> +
> +		if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
> +			/*
> +			 * Here we add two extra NOOPs as padding to avoid
> +			 * lite restore of a context with HEAD==TAIL.
> +			 */
> +			intel_logical_ring_emit(ringbuf, MI_NOOP);
> +			intel_logical_ring_emit(ringbuf, MI_NOOP);
> +			intel_logical_ring_advance(ringbuf);
> +		}

But you are still doing the dance here inside gem, not as a quirk of the
backend. This can be moved to advance_and_submit - needs to since
otherwise the logic is now split between two "independent" units.
-Chris
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6192
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  301/301              301/301
SNB                                  316/316              316/316
IVB                 -1              328/328              327/328
BYT                                  285/285              285/285
HSW                                  394/394              394/394
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 IVB  igt@gem_pwrite_pread@uncached-copy-performance      DMESG_WARN(3)PASS(8)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck timer elapsed... blitter ring idle
Note: You need to pay more attention to line start with '*'