drm/i915/chv: Implement WaDisableShadowRegForCpd

Submitted by deepak.s@linux.intel.com on April 14, 2015, 10:28 a.m.

Details

Message ID 1429007334-31245-1-git-send-email-deepak.s@linux.intel.com
State New
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Commit Message

deepak.s@linux.intel.com April 14, 2015, 10:28 a.m.
From: Deepak S <deepak.s@linux.intel.com>

This WA disable usage of shadow register during CPD/RC6 transactions on
CHV

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 2 files changed, 5 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c97842..bcdb16b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6206,6 +6206,7 @@  enum skl_disp_power_wells {
 #define  GTFIFOCTL				0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
+#define GT_FIFO_CTL_BLOCK_POLICY	(3<<11)
 
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4dd8b41..b9d3c00 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6431,6 +6431,10 @@  static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSDEUnitClockGating:chv */
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+	/* WaDisableShadowRegForCpd */
+	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
+						  GT_FIFO_CTL_BLOCK_POLICY);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)

Comments

On Tue, Apr 14, 2015 at 03:58:54PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> 
> This WA disable usage of shadow register during CPD/RC6 transactions on
> CHV

I suppose is a workaround for the shadow vs. wake FIFO problem... Yeah
hsd seems to agree (after a bit of extra digging).

> 
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c97842..bcdb16b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
>  #define  GTFIFOCTL				0x120008
>  #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
>  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
> +#define GT_FIFO_CTL_BLOCK_POLICY	(3<<11)

GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)

perhaps?

>  
>  #define  HSW_IDICR				0x9008
>  #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4dd8b41..b9d3c00 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableSDEUnitClockGating:chv */
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaDisableShadowRegForCpd */
> +	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
> +						  GT_FIFO_CTL_BLOCK_POLICY);

I think __intel_uncore_early_sanitize() might be a better place for
this.

>  }
>  
>  static void g4x_init_clock_gating(struct drm_device *dev)
> -- 
> 1.9.1
On Tuesday 14 April 2015 04:29 PM, Ville Syrjälä wrote:
> On Tue, Apr 14, 2015 at 03:58:54PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> This WA disable usage of shadow register during CPD/RC6 transactions on
>> CHV
> I suppose is a workaround for the shadow vs. wake FIFO problem... Yeah
> hsd seems to agree (after a bit of extra digging).

Yes ville, this WA is avoid problem between shadow vs wake FIFO unload problem.
I will address the comments and send new patch set

>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 9c97842..bcdb16b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6206,6 +6206,7 @@ enum skl_disp_power_wells {
>>   #define  GTFIFOCTL				0x120008
>>   #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
>>   #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
>> +#define GT_FIFO_CTL_BLOCK_POLICY	(3<<11)
> GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL	(1 << 12)
> GT_FIFO_CTL_RC6_POLICY_STALL		(1 << 11)
>
> perhaps?

>>   
>>   #define  HSW_IDICR				0x9008
>>   #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4dd8b41..b9d3c00 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6431,6 +6431,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>>   	/* WaDisableSDEUnitClockGating:chv */
>>   	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>>   		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> +
>> +	/* WaDisableShadowRegForCpd */
>> +	I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
>> +						  GT_FIFO_CTL_BLOCK_POLICY);
> I think __intel_uncore_early_sanitize() might be a better place for
> this.
>
>>   }
>>   
>>   static void g4x_init_clock_gating(struct drm_device *dev)
>> -- 
>> 1.9.1