[v2,1/1] drm/i915: Disable Render power gating

Submitted by Sagar Arun Kamble on April 12, 2015, 5:58 a.m.

Details

Message ID 1428818294-12727-1-git-send-email-sagar.a.kamble@intel.com
State New
Headers show

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Commit Message

Sagar Arun Kamble April 12, 2015, 5:58 a.m.
From: Sagar Kamble <sagar.a.kamble@intel.com>

When RC6 along with Render power gating is enabled, GPU hang
happens due to lack of synchronization between GTI and Render
power gating.

v2: Updated commit message and WA name (Damien)

Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9975401..4dd8b41 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4350,9 +4350,12 @@  static void gen9_enable_rc6(struct drm_device *dev)
 				   GEN6_RC_CTL_EI_MODE(1) |
 				   rc6_mask);
 
-	/* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+	/*
+	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
+	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+	 */
 	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
-			(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+			GEN9_MEDIA_PG_ENABLE : 0);
 
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

Comments

On Sun, Apr 12, 2015 at 11:28:14AM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
> 
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render
> power gating.
> 
> v2: Updated commit message and WA name (Damien)
> 
> Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>

Queued for -next, thanks for the patch.
-Daniel