| Message ID | 20210708211827.288601-6-jose.souza@intel.com |
|---|---|
| State | Accepted |
| Commit | d4bc18183ee1453e550a3f4cbec0c1ea15999e61 |
| Headers | show |
| Series |
"Series without cover letter"
( rev:
1
)
in
Intel GFX |
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 65ddb6ca16e67..fe380896eb99e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); } -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 val; - val = MBUS_DBOX_A_CREDIT(2); + /* Wa_22010947358:adl-p */ + if (IS_ALDERLAKE_P(dev_priv)) + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); + else + val = MBUS_DBOX_A_CREDIT(2); if (DISPLAY_VER(dev_priv) >= 12) { val |= MBUS_DBOX_BW_CREDIT(2); @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (dev_priv->display.initial_watermarks) dev_priv->display.initial_watermarks(state, crtc); - if (DISPLAY_VER(dev_priv) >= 11) - icl_pipe_mbus_enable(crtc); + if (DISPLAY_VER(dev_priv) >= 11) { + const struct intel_dbuf_state *dbuf_state = + intel_atomic_get_new_dbuf_state(state); + + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); + } if (new_crtc_state->bigjoiner_slave) intel_crtc_vblank_on(new_crtc_state);
On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote: > Alderlake-P have different values for MBUS DBOX A credits depending > if MBUS join is enabled or not. > > BSpec: 50343 > BSpec: 54369 > Cc: Matt Atwood <matthew.s.atwood@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 65ddb6ca16e67..fe380896eb99e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); > } > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > u32 val; > > - val = MBUS_DBOX_A_CREDIT(2); > + /* Wa_22010947358:adl-p */ > + if (IS_ALDERLAKE_P(dev_priv)) > + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); > + else > + val = MBUS_DBOX_A_CREDIT(2); If we're in single-pipe / joined-mbus mode, then we'll program the credits to 6. If we later turn on another pipe, reallocate the DDB, and turn off joined-mbus mode, we'll set that other pipe's credits to 4 during the sequence of hsw_crtc_enable() -> icl_pipe_mbus_enable(). But don't we also need to go back re-program the credits down to 4 on the first pipe too (which is already enabled and won't be re-calling hsw_crtc_enable())? I might be missing something; it's been a while since I really looked at any of the dbuf stuff... Matt > > if (DISPLAY_VER(dev_priv) >= 12) { > val |= MBUS_DBOX_BW_CREDIT(2); > @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > if (dev_priv->display.initial_watermarks) > dev_priv->display.initial_watermarks(state, crtc); > > - if (DISPLAY_VER(dev_priv) >= 11) > - icl_pipe_mbus_enable(crtc); > + if (DISPLAY_VER(dev_priv) >= 11) { > + const struct intel_dbuf_state *dbuf_state = > + intel_atomic_get_new_dbuf_state(state); > + > + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); > + } > > if (new_crtc_state->bigjoiner_slave) > intel_crtc_vblank_on(new_crtc_state); > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, 2021-07-09 at 22:41 -0700, Matt Roper wrote: > On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote: > > Alderlake-P have different values for MBUS DBOX A credits depending > > if MBUS join is enabled or not. > > > > BSpec: 50343 > > BSpec: 54369 > > Cc: Matt Atwood <matthew.s.atwood@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 65ddb6ca16e67..fe380896eb99e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); > > } > > > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) > > { > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > enum pipe pipe = crtc->pipe; > > u32 val; > > > > - val = MBUS_DBOX_A_CREDIT(2); > > + /* Wa_22010947358:adl-p */ > > + if (IS_ALDERLAKE_P(dev_priv)) > > + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); > > + else > > + val = MBUS_DBOX_A_CREDIT(2); > > If we're in single-pipe / joined-mbus mode, then we'll program the > credits to 6. If we later turn on another pipe, reallocate the DDB, and > turn off joined-mbus mode, we'll set that other pipe's credits to 4 > during the sequence of hsw_crtc_enable() -> icl_pipe_mbus_enable(). But > don't we also need to go back re-program the credits down to 4 on the > first pipe too (which is already enabled and won't be re-calling > hsw_crtc_enable())? > > I might be missing something; it's been a while since I really looked at > any of the dbuf stuff... skl_compute_ddb() is handling this cases, it will force a modeset in all pipes in cases like this. > > > Matt > > > > > if (DISPLAY_VER(dev_priv) >= 12) { > > val |= MBUS_DBOX_BW_CREDIT(2); > > @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > if (dev_priv->display.initial_watermarks) > > dev_priv->display.initial_watermarks(state, crtc); > > > > - if (DISPLAY_VER(dev_priv) >= 11) > > - icl_pipe_mbus_enable(crtc); > > + if (DISPLAY_VER(dev_priv) >= 11) { > > + const struct intel_dbuf_state *dbuf_state = > > + intel_atomic_get_new_dbuf_state(state); > > + > > + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); > > + } > > > > if (new_crtc_state->bigjoiner_slave) > > intel_crtc_vblank_on(new_crtc_state); > > -- > > 2.32.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Tue, Aug 03, 2021 at 01:19:12PM -0700, Souza, Jose wrote: > On Fri, 2021-07-09 at 22:41 -0700, Matt Roper wrote: > > On Thu, Jul 08, 2021 at 02:18:26PM -0700, José Roberto de Souza wrote: > > > Alderlake-P have different values for MBUS DBOX A credits depending > > > if MBUS join is enabled or not. > > > > > > BSpec: 50343 > > > BSpec: 54369 > > > Cc: Matt Atwood <matthew.s.atwood@intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- > > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index 65ddb6ca16e67..fe380896eb99e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -3400,13 +3400,17 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, > > > intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); > > > } > > > > > > -static void icl_pipe_mbus_enable(struct intel_crtc *crtc) > > > +static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus) > > > { > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > enum pipe pipe = crtc->pipe; > > > u32 val; > > > > > > - val = MBUS_DBOX_A_CREDIT(2); > > > + /* Wa_22010947358:adl-p */ > > > + if (IS_ALDERLAKE_P(dev_priv)) > > > + val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); > > > + else > > > + val = MBUS_DBOX_A_CREDIT(2); > > > > If we're in single-pipe / joined-mbus mode, then we'll program the > > credits to 6. If we later turn on another pipe, reallocate the DDB, and > > turn off joined-mbus mode, we'll set that other pipe's credits to 4 > > during the sequence of hsw_crtc_enable() -> icl_pipe_mbus_enable(). But > > don't we also need to go back re-program the credits down to 4 on the > > first pipe too (which is already enabled and won't be re-calling > > hsw_crtc_enable())? > > > > I might be missing something; it's been a while since I really looked at > > any of the dbuf stuff... > > skl_compute_ddb() is handling this cases, it will force a modeset in all pipes in cases like this. > Ah, that's right. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > > > > > Matt > > > > > > > > if (DISPLAY_VER(dev_priv) >= 12) { > > > val |= MBUS_DBOX_BW_CREDIT(2); > > > @@ -3561,8 +3565,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > > if (dev_priv->display.initial_watermarks) > > > dev_priv->display.initial_watermarks(state, crtc); > > > > > > - if (DISPLAY_VER(dev_priv) >= 11) > > > - icl_pipe_mbus_enable(crtc); > > > + if (DISPLAY_VER(dev_priv) >= 11) { > > > + const struct intel_dbuf_state *dbuf_state = > > > + intel_atomic_get_new_dbuf_state(state); > > > + > > > + icl_pipe_mbus_enable(crtc, dbuf_state->joined_mbus); > > > + } > > > > > > if (new_crtc_state->bigjoiner_slave) > > > intel_crtc_vblank_on(new_crtc_state); > > > -- > > > 2.32.0 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > >
Alderlake-P have different values for MBUS DBOX A credits depending if MBUS join is enabled or not. BSpec: 50343 BSpec: 54369 Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-)