[v4] drm/i915: Initialize workarounds in logical ring mode too

Submitted by Michel Thierry on Nov. 11, 2014, 4:47 p.m.

Details

Message ID 1415724453-21648-1-git-send-email-michel.thierry@intel.com
State New, archived
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Commit Message

Michel Thierry Nov. 11, 2014, 4:47 p.m.
Following the legacy ring submission example, update the
ring->init_context() hook to support the execlist submission mode.

v2: update to use the new workaround macros and cleanup unused code.
This takes care of both bdw and chv workarounds.

v2.1: Add missing call to init_context() during deferred context creation.

v3: Split init_context (emit) in legacy/lrc modes. For lrc, get the ringbuf
from the context (Mika/Daniel).

v4: Merge init_context interfaces back, the legacy mode only needs the ring,
but the lrc mode needs the ring and context (Mika).

Issue: VIZ-4092
Issue: GMIN-3475
Change-Id: Ie3d093b2542ab0e2a44b90460533e2f979788d6c
Cc: Deepak S <deepak.s@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
 drivers/gpu/drm/i915/intel_lrc.c        | 47 ++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  5 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++-
 4 files changed, 54 insertions(+), 5 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index c4dac19..d7e7247 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -663,7 +663,7 @@  done:
 
 	if (uninitialized) {
 		if (ring->init_context) {
-			ret = ring->init_context(ring);
+			ret = ring->init_context(ring, to);
 			if (ret)
 				DRM_ERROR("ring init context: %d\n", ret);
 		}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 78c3dfc..cb3bc11 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1072,6 +1072,44 @@  int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
 	return 0;
 }
 
+static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
+	       struct intel_context *ctx)
+{
+	int ret, i;
+	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
+	struct drm_device *dev = ring->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct i915_workarounds *w = &dev_priv->workarounds;
+
+	if (WARN_ON(w->count == 0))
+		return 0;
+
+	ring->gpu_caches_dirty = true;
+	ret = logical_ring_flush_all_caches(ringbuf);
+	if (ret)
+		return ret;
+
+	ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2);
+	if (ret)
+		return ret;
+
+	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
+	for (i = 0; i < w->count; i++) {
+		intel_logical_ring_emit(ringbuf, w->reg[i].addr);
+		intel_logical_ring_emit(ringbuf, w->reg[i].value);
+	}
+	intel_logical_ring_emit(ringbuf, MI_NOOP);
+
+	intel_logical_ring_advance(ringbuf);
+
+	ring->gpu_caches_dirty = true;
+	ret = logical_ring_flush_all_caches(ringbuf);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static int gen8_init_common_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
@@ -1115,7 +1153,7 @@  static int gen8_init_render_ring(struct intel_engine_cs *ring)
 
 	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-	return ret;
+	return init_workarounds_ring(ring);
 }
 
 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
@@ -1366,6 +1404,7 @@  static int logical_render_ring_init(struct drm_device *dev)
 		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
 	ring->init = gen8_init_render_ring;
+	ring->init_context = intel_logical_ring_workarounds_emit;
 	ring->cleanup = intel_fini_pipe_control;
 	ring->get_seqno = gen8_get_seqno;
 	ring->set_seqno = gen8_set_seqno;
@@ -1870,6 +1909,12 @@  int intel_lr_context_deferred_create(struct intel_context *ctx,
 	}
 
 	if (ring->id == RCS && !ctx->rcs_initialized) {
+		if (ring->init_context) {
+			ret = ring->init_context(ring, ctx);
+			if (ret)
+				DRM_ERROR("ring init context: %d\n", ret);
+		}
+
 		ret = intel_lr_context_render_state_init(ring, ctx);
 		if (ret) {
 			DRM_ERROR("Init render state failed: %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 98f2787..9e17432 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -677,7 +677,8 @@  err:
 	return ret;
 }
 
-static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
+static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
+		struct intel_context *ctx)
 {
 	int ret, i;
 	struct drm_device *dev = ring->dev;
@@ -818,7 +819,7 @@  static int chv_init_workarounds(struct intel_engine_cs *ring)
 	return 0;
 }
 
-static int init_workarounds_ring(struct intel_engine_cs *ring)
+int init_workarounds_ring(struct intel_engine_cs *ring)
 {
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f0e7761..86c4447 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -148,7 +148,8 @@  struct  intel_engine_cs {
 
 	int		(*init)(struct intel_engine_cs *ring);
 
-	int		(*init_context)(struct intel_engine_cs *ring);
+	int		(*init_context)(struct intel_engine_cs *ring,
+				      struct intel_context *ctx);
 
 	void		(*write_tail)(struct intel_engine_cs *ring,
 				      u32 value);
@@ -429,6 +430,8 @@  int intel_init_vebox_ring_buffer(struct drm_device *dev);
 u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
 void intel_ring_setup_status_page(struct intel_engine_cs *ring);
 
+int init_workarounds_ring(struct intel_engine_cs *ring);
+
 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
 {
 	return ringbuf->tail;

Comments

Michel Thierry <michel.thierry@intel.com> writes:

> Following the legacy ring submission example, update the
> ring->init_context() hook to support the execlist submission mode.
>
> v2: update to use the new workaround macros and cleanup unused code.
> This takes care of both bdw and chv workarounds.
>
> v2.1: Add missing call to init_context() during deferred context creation.
>
> v3: Split init_context (emit) in legacy/lrc modes. For lrc, get the ringbuf
> from the context (Mika/Daniel).
>
> v4: Merge init_context interfaces back, the legacy mode only needs the ring,
> but the lrc mode needs the ring and context (Mika).
>
> Issue: VIZ-4092
> Issue: GMIN-3475
> Change-Id: Ie3d093b2542ab0e2a44b90460533e2f979788d6c
> Cc: Deepak S <deepak.s@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_context.c |  2 +-
>  drivers/gpu/drm/i915/intel_lrc.c        | 47 ++++++++++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_ringbuffer.c |  5 ++--
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++-
>  4 files changed, 54 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index c4dac19..d7e7247 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -663,7 +663,7 @@ done:
>  
>  	if (uninitialized) {
>  		if (ring->init_context) {
> -			ret = ring->init_context(ring);
> +			ret = ring->init_context(ring, to);
>  			if (ret)
>  				DRM_ERROR("ring init context: %d\n", ret);
>  		}
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 78c3dfc..cb3bc11 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1072,6 +1072,44 @@ int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
>  	return 0;
>  }
>  
> +static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
> +	       struct intel_context *ctx)
> +{
> +	int ret, i;
> +	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
> +	struct drm_device *dev = ring->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct i915_workarounds *w = &dev_priv->workarounds;
> +
> +	if (WARN_ON(w->count == 0))
> +		return 0;
> +
> +	ring->gpu_caches_dirty = true;
> +	ret = logical_ring_flush_all_caches(ringbuf);
> +	if (ret)
> +		return ret;
> +
> +	ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2);
> +	if (ret)
> +		return ret;
> +
> +	intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
> +	for (i = 0; i < w->count; i++) {
> +		intel_logical_ring_emit(ringbuf, w->reg[i].addr);
> +		intel_logical_ring_emit(ringbuf, w->reg[i].value);
> +	}
> +	intel_logical_ring_emit(ringbuf, MI_NOOP);
> +
> +	intel_logical_ring_advance(ringbuf);
> +
> +	ring->gpu_caches_dirty = true;
> +	ret = logical_ring_flush_all_caches(ringbuf);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
>  static int gen8_init_common_ring(struct intel_engine_cs *ring)
>  {
>  	struct drm_device *dev = ring->dev;
> @@ -1115,7 +1153,7 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
>  
>  	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>  
> -	return ret;
> +	return init_workarounds_ring(ring);
>  }
>  
>  static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
> @@ -1366,6 +1404,7 @@ static int logical_render_ring_init(struct drm_device *dev)
>  		ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>  
>  	ring->init = gen8_init_render_ring;
> +	ring->init_context = intel_logical_ring_workarounds_emit;
>  	ring->cleanup = intel_fini_pipe_control;
>  	ring->get_seqno = gen8_get_seqno;
>  	ring->set_seqno = gen8_set_seqno;
> @@ -1870,6 +1909,12 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
>  	}
>  
>  	if (ring->id == RCS && !ctx->rcs_initialized) {
> +		if (ring->init_context) {
> +			ret = ring->init_context(ring, ctx);
> +			if (ret)
> +				DRM_ERROR("ring init context: %d\n", ret);
> +		}
> +
>  		ret = intel_lr_context_render_state_init(ring, ctx);
>  		if (ret) {
>  			DRM_ERROR("Init render state failed: %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 98f2787..9e17432 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -677,7 +677,8 @@ err:
>  	return ret;
>  }
>  
> -static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
> +static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
> +		struct intel_context *ctx)
>  {
>  	int ret, i;
>  	struct drm_device *dev = ring->dev;
> @@ -818,7 +819,7 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  	return 0;
>  }
>  
> -static int init_workarounds_ring(struct intel_engine_cs *ring)
> +int init_workarounds_ring(struct intel_engine_cs *ring)
>  {
>  	struct drm_device *dev = ring->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index f0e7761..86c4447 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -148,7 +148,8 @@ struct  intel_engine_cs {
>  
>  	int		(*init)(struct intel_engine_cs *ring);
>  
> -	int		(*init_context)(struct intel_engine_cs *ring);
> +	int		(*init_context)(struct intel_engine_cs *ring,
> +				      struct intel_context *ctx);
>  
>  	void		(*write_tail)(struct intel_engine_cs *ring,
>  				      u32 value);
> @@ -429,6 +430,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev);
>  u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
>  void intel_ring_setup_status_page(struct intel_engine_cs *ring);
>  
> +int init_workarounds_ring(struct intel_engine_cs *ring);
> +
>  static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
>  {
>  	return ringbuf->tail;
> -- 
> 2.1.1
On Tue, Nov 11, 2014 at 06:59:52PM +0200, Mika Kuoppala wrote:
> Michel Thierry <michel.thierry@intel.com> writes:
> 
> > Following the legacy ring submission example, update the
> > ring->init_context() hook to support the execlist submission mode.
> >
> > v2: update to use the new workaround macros and cleanup unused code.
> > This takes care of both bdw and chv workarounds.
> >
> > v2.1: Add missing call to init_context() during deferred context creation.
> >
> > v3: Split init_context (emit) in legacy/lrc modes. For lrc, get the ringbuf
> > from the context (Mika/Daniel).
> >
> > v4: Merge init_context interfaces back, the legacy mode only needs the ring,
> > but the lrc mode needs the ring and context (Mika).

Cool, revised version already on the m-l, pls ignore my other reply ;-)

> >
> > Issue: VIZ-4092
> > Issue: GMIN-3475
> > Change-Id: Ie3d093b2542ab0e2a44b90460533e2f979788d6c
> > Cc: Deepak S <deepak.s@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Queued for -next, thanks for the patch.
-Daniel
On Tue, Nov 11, 2014 at 04:47:33PM +0000, Michel Thierry wrote:
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 98f2787..9e17432 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -677,7 +677,8 @@ err:
>  	return ret;
>  }
>  
> -static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
> +static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
> +		struct intel_context *ctx)

One nitpick for the future: We align continuation lines for paramter lists
to the opening (. checkpatch.pl --strict will catch this for you. I've
fixed this while applying since it disturbed my ocd too much ;-)
-Daniel
>  {
>  	int ret, i;
>  	struct drm_device *dev = ring->dev;
> @@ -818,7 +819,7 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  	return 0;
>  }
>  
> -static int init_workarounds_ring(struct intel_engine_cs *ring)
> +int init_workarounds_ring(struct intel_engine_cs *ring)
>  {
>  	struct drm_device *dev = ring->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index f0e7761..86c4447 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -148,7 +148,8 @@ struct  intel_engine_cs {
>  
>  	int		(*init)(struct intel_engine_cs *ring);
>  
> -	int		(*init_context)(struct intel_engine_cs *ring);
> +	int		(*init_context)(struct intel_engine_cs *ring,
> +				      struct intel_context *ctx);
>  
>  	void		(*write_tail)(struct intel_engine_cs *ring,
>  				      u32 value);
> @@ -429,6 +430,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev);
>  u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
>  void intel_ring_setup_status_page(struct intel_engine_cs *ring);
>  
> +int init_workarounds_ring(struct intel_engine_cs *ring);
> +
>  static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
>  {
>  	return ringbuf->tail;
> -- 
> 2.1.1
>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=247/348->277/348
PNV: pass/total=326/328->324/328
ILK: pass/total=329/330->328/330
IVB: pass/total=544/546->544/546
SNB: pass/total=558/563->561/563
HSW: pass/total=586/591->587/591
BDW: pass/total=435/435->433/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-basic, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-capture-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-debugfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_drv_hangman_error-state-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_ban-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M38) -> DMESG_WARN(1, M31)PASS(3, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M29M38M36) -> DMESG_WARN(2, M31)PASS(2, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-blt, BLACKLIST(1, M31)DMESG_WARN(11, M31M36M29)PASS(13, M31M36M29M38) -> DMESG_WARN(2, M31)PASS(2, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-bsd, BLACKLIST(1, M31)DMESG_WARN(12, M31M36M29)PASS(12, M31M36M29M38) -> DMESG_WARN(2, M31)PASS(2, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-blt, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-bsd, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-fork-reverse-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_close-pending-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_params-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-blt, BLACKLIST(1, M31)DMESG_WARN(16, M31M36M29)PASS(8, M29M38M36) -> DMESG_WARN(2, M31)PASS(2, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-bsd, BLACKLIST(1, M31)DMESG_WARN(14, M31M36M29)PASS(10, M36M38M29) -> DMESG_WARN(1, M31)PASS(3, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-count-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-blt, BLACKLIST(1, M31)DMESG_WARN(8, M36M29M31)PASS(16, M31M36M29M38) -> DMESG_WARN(1, M31)PASS(3, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-bsd, BLACKLIST(1, M31)DMESG_WARN(9, M36M29M31)PASS(15, M31M36M29M38) -> DMESG_WARN(1, M31)PASS(3, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_reset-stats-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_gem_reset_stats_unrelated-ctx-render, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
BYT: Intel_gpu_tools, igt_drv_hangman_ring-stop-sysfs-entry, BLACKLIST(1, M31)PASS(24, M31M36M29M38) -> PASS(4, M31)
PNV: Intel_gpu_tools, igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible, PASS(7, M25M7) -> DMESG_WARN(1, M25)PASS(3, M25)
PNV: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, DMESG_WARN(1, M25)TIMEOUT(15, M7M25M24M23)PASS(3, M24) -> DMESG_WARN(3, M25)TIMEOUT(1, M25)
PNV: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-interruptible, PASS(7, M25) -> DMESG_WARN(1, M25)PASS(3, M25)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-modeset-interruptible, DMESG_WARN(2, M26)PASS(26, M37M26M6) -> PASS(4, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-panning-vs-hang, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_wf_vblank-vs-modeset, DMESG_WARN(1, M26)PASS(3, M26) -> DMESG_WARN(2, M26)PASS(2, M26)
IVB: Intel_gpu_tools, igt_kms_plane_plane-position-covered-pipe-A-plane-1, TIMEOUT(1, M34)PASS(27, M21M4M34) -> PASS(4, M21)
IVB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M34M21M4)PASS(1, M34) -> TIMEOUT(1, M21)PASS(3, M21)
SNB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M35) -> TIMEOUT(1, M22)PASS(3, M22)
SNB: Intel_gpu_tools, igt_pm_rpm_legacy-planes, TIMEOUT(1, M35) -> TIMEOUT(3, M22)PASS(1, M22)
SNB: Intel_gpu_tools, igt_pm_rpm_legacy-planes-dpms, TIMEOUT(1, M35) -> TIMEOUT(3, M22)PASS(1, M22)
SNB: Intel_gpu_tools, igt_pm_rpm_universal-planes, TIMEOUT(1, M35) -> TIMEOUT(2, M22)PASS(1, M22)
SNB: Intel_gpu_tools, igt_pm_rpm_universal-planes-dpms, TIMEOUT(1, M35) -> PASS(1, M22)
HSW: Intel_gpu_tools, igt_kms_cursor_crc_cursor-64x64-offscreen, PASS(1, M40) -> DMESG_WARN(2, M39)PASS(2, M39)
HSW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS(1, M40) -> TIMEOUT(1, M39)PASS(3, M39)
HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes, TIMEOUT(1, M40) -> TIMEOUT(3, M39)PASS(1, M39)
HSW: Intel_gpu_tools, igt_pm_rpm_legacy-planes-dpms, TIMEOUT(1, M40) -> TIMEOUT(3, M39)PASS(1, M39)
HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes, TIMEOUT(1, M40) -> TIMEOUT(2, M39)PASS(1, M39)
HSW: Intel_gpu_tools, igt_pm_rpm_universal-planes-dpms, TIMEOUT(1, M40) -> PASS(1, M39)
HSW: Intel_gpu_tools, igt_kms_flip_dpms-off-confusion, PASS(1, M40) -> DMESG_WARN(1, M39)
BDW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(15, M28M42M30)PASS(1, M42) -> TIMEOUT(1, M28)PASS(3, M28)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, PASS(31, M42M30M28) -> DMESG_WARN(1, M28)PASS(3, M28)