[v2,03/11] drm/amdgpu: define the TMZ bit for the PTE

Submitted by Huang, Ray on Sept. 25, 2019, 1:45 p.m.

Details

Message ID 1569419090-5304-4-git-send-email-ray.huang@amd.com
State New
Headers show
Series "drm/amdgpu: introduce secure buffer object support (trusted memory zone)" ( rev: 2 ) in DRI devel

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Commit Message

Huang, Ray Sept. 25, 2019, 1:45 p.m.
From: Alex Deucher <alexander.deucher@amd.com>

Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++
 1 file changed, 3 insertions(+)

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diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 3352a87..4b5d283 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -53,6 +53,9 @@  struct amdgpu_bo_list_entry;
 #define AMDGPU_PTE_SYSTEM	(1ULL << 1)
 #define AMDGPU_PTE_SNOOPED	(1ULL << 2)
 
+/* RV+ */
+#define AMDGPU_PTE_TMZ		(1ULL << 3)
+
 /* VI only */
 #define AMDGPU_PTE_EXECUTABLE	(1ULL << 4)