[v7,5/5] drm/mediatek: config mipitx impedance with calibration data

Submitted by Jitao Shi on Sept. 20, 2019, 9:04 a.m.

Details

Message ID 20190920090432.3308-6-jitao.shi@mediatek.com
State New
Headers show
Series "Support mipitx for mt8183" ( rev: 4 ) in DRI devel

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Commit Message

Jitao Shi Sept. 20, 2019, 9:04 a.m.
Config mipitx impedance with calibration data to make sure their impedance
are 100ohm.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_mipi_tx.h        |  1 +
 drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 63 +++++++++++++++++++
 2 files changed, 64 insertions(+)

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diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
index eea44327fe9f..a1b6292145de 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h
@@ -28,6 +28,7 @@  struct mtk_mipi_tx {
 	void __iomem *regs;
 	u32 data_rate;
 	u32 mipitx_drive;
+	u32 rt_code[5];
 	const struct mtk_mipitx_data *driver_data;
 	struct clk_hw pll_hw;
 	struct clk *pll;
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
index 5bda8355145f..9ca90dee095a 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c
@@ -5,6 +5,8 @@ 
  */
 
 #include "mtk_mipi_tx.h"
+#include <linux/nvmem-consumer.h>
+#include <linux/slab.h>
 
 #define MIPITX_LANE_CON		0x000c
 #define RG_DSI_CPHY_T1DRV_EN		BIT(0)
@@ -28,6 +30,7 @@ 
 #define MIPITX_PLL_CON4	0x003c
 #define RG_DSI_PLL_IBIAS		(3 << 10)
 
+#define MIPITX_D2P_RTCODE	0x0100
 #define MIPITX_D2_SW_CTL_EN	0x0144
 #define MIPITX_D0_SW_CTL_EN	0x0244
 #define MIPITX_CK_CKMODE_EN	0x0328
@@ -108,6 +111,64 @@  static const struct clk_ops mtk_mipi_tx_pll_ops = {
 	.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
 };
 
+static int mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+	u32 *buf = NULL;
+	int i, j;
+	struct nvmem_cell *cell;
+	struct device *dev = mipi_tx->dev;
+	size_t len;
+
+	cell = nvmem_cell_get(dev, "calibration-data");
+	if (IS_ERR(cell)) {
+		dev_warn(dev, "nvmem_cell_get fail\n");
+		return -EINVAL;
+	}
+
+	buf = (u32 *)nvmem_cell_read(cell, &len);
+
+	nvmem_cell_put(cell);
+
+	if (IS_ERR(buf)) {
+		dev_warn(dev, "can't get data\n");
+		return -EINVAL;
+	}
+
+	if (len < 3 * sizeof(u32)) {
+		dev_warn(dev, "invalid calibration data\n");
+		kfree(buf);
+		return -EINVAL;
+	}
+
+	mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1F) << 5) |
+			      (buf[0] >> 11 & 0x1F);
+	mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1F) << 5) |
+			      (buf[0] >> 1 & 0x1F);
+	mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1F) << 5) |
+			      (buf[1] >> 22 & 0x1F);
+	mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1F) << 5) |
+			      (buf[1] >> 12 & 0x1F);
+	mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1F) << 5) |
+			      (buf[1] >> 2 & 0x1F);
+
+	for (i = 0; i < 5; i++) {
+		if ((mipi_tx->rt_code[i] & 0x1F) == 0)
+			mipi_tx->rt_code[i] |= 0x10;
+
+		if ((mipi_tx->rt_code[i] >> 5 & 0x1F) == 0)
+			mipi_tx->rt_code[i] |= 0x10 << 5;
+
+		for (j = 0; j < 10; j++) {
+			mtk_mipi_tx_update_bits(mipi_tx,
+				MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+				1, mipi_tx->rt_code[i] >> j & 1);
+		}
+	}
+
+	kfree(buf);
+	return 0;
+}
+
 static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 {
 	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
@@ -130,6 +191,8 @@  static void mtk_mipi_tx_power_on_signal(struct phy *phy)
 				RG_DSI_HSTX_LDO_REF_SEL,
 				mipi_tx->mipitx_drive << 6);
 
+	mtk_mipi_tx_config_calibration_data(mipi_tx);
+
 	mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
 }