[4/4] drm/amdgpu: implement ras query function for pcie bif

Submitted by Zhang, Hawking on Sept. 11, 2019, 3:23 a.m.

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Message ID DM5PR12MB1418272EF377973FAE740FFDFCB10@DM5PR12MB1418.namprd12.prod.outlook.com
State New
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Series "drm/amdgpu: add pcie bif ras query functionality" ( rev: 2 ) in AMD X.Org drivers

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Commit Message

Zhang, Hawking Sept. 11, 2019, 3:23 a.m.
Series is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>


Regards,
Hawking
-----Original Message-----
From: Chen, Guchun <Guchun.Chen@amd.com> 

Sent: 2019年9月11日 11:21
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang@amd.com>; Li, Dennis <Dennis.Li@amd.com>; Zhou1, Tao <Tao.Zhou1@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
Cc: Li, Candice <Candice.Li@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Zhou1, Tao <Tao.Zhou1@amd.com>
Subject: [PATCH 4/4] drm/amdgpu: implement ras query function for pcie bif

ras error query funtionality implementation

Change-Id: Id7d8c35621960685a2a7507e4e95939f5a05bdc6
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>

Signed-off-by: Guchun Chen <guchun.chen@amd.com>

---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 30 ++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

2.17.1

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index fa6a8918dc8c..b776332d979f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -476,6 +476,36 @@  static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *a  static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
 					void *ras_error_status)
 {
+	uint32_t global_sts, central_sts, int_eoi;
+	uint32_t corr, fatal, non_fatal;
+	struct ras_err_data *err_data = (struct ras_err_data 
+*)ras_error_status;
+
+	global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
+	corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
+	fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
+	non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
+				ParityErrNonFatal);
+
+	if (corr)
+		err_data->ce_count++;
+	if (fatal)
+		err_data->ue_count++;
+
+	if (corr || fatal || non_fatal) {
+		central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
+		/* clear error status register */
+		WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
+
+		if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
+				BIFL_RasContller_Intr_Recv)) {
+			/* clear interrupt status register */
+			WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
+			int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
+			int_eoi = REG_SET_FIELD(int_eoi,
+					IOHC_INTERRUPT_EOI, SMI_EOI, 1);
+			WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
+		}
+	}
 }
 
 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
--