[v2,05/17] drm/i915: Bump frame start delay to max

Submitted by Ville Syrjälä on Sept. 10, 2019, 4:08 p.m.

Details

Message ID 20190910160819.11529-5-ville.syrjala@linux.intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Ville Syrjälä Sept. 10, 2019, 4:08 p.m.
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The only time we can safely update single buffered registers
(such as plane/pipe gamma, plane color correction) is between
start of vblank and frame start. At frame start the pipe will
already start to process the pixels for the subsequent frame
and so any register update after that point is likely to cause
visible artifacts.

Currently we have configured the frame start delay to its minimum
value (~1 scanline). Bump it to the max (~4 scanlines) to give us
a bit more time to update those registers without causing visible
artifacts.

Unfortunately the gamma LUTs can be rather huge so this is still
not enough time in many so probably not worth the hassle. Also
frame start delay is generally tagged as "test mode" in the spec
so not sure we should be extending it at all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e2d6d8af7b4f..01ed591851e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1642,7 +1642,7 @@  static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
 		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 		/* configure frame start delay to match the CPU */
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+		val |= TRANS_CHICKEN2_FRAME_START_DELAY(3);
 		I915_WRITE(reg, val);
 	}
 
@@ -1653,7 +1653,7 @@  static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
 	if (HAS_PCH_IBX(dev_priv)) {
 		/* configure frame start delay to match the CPU */
 		val &= ~TRANS_FRAME_START_DELAY_MASK;
-		val |= TRANS_FRAME_START_DELAY(0);
+		val |= TRANS_FRAME_START_DELAY(3);
 
 		/*
 		 * Make the BPC in transcoder be consistent with
@@ -1697,7 +1697,7 @@  static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
 	/* configure frame start delay to match the CPU */
 	val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-	val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+	val |= TRANS_CHICKEN2_FRAME_START_DELAY(3);
 	I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
 
 	val = TRANS_ENABLE;
@@ -6443,7 +6443,7 @@  static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
 
 	val = I915_READ(reg);
 	val &= ~HSW_FRAME_START_DELAY_MASK;
-	val |= HSW_FRAME_START_DELAY(0);
+	val |= HSW_FRAME_START_DELAY(3);
 	I915_WRITE(reg, val);
 }
 
@@ -8340,7 +8340,7 @@  static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
-	pipeconf |= PIPECONF_FRAME_START_DELAY(0);
+	pipeconf |= PIPECONF_FRAME_START_DELAY(3);
 
 	I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
 	POSTING_READ(PIPECONF(crtc->pipe));
@@ -9434,7 +9434,7 @@  static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
-	val |= PIPECONF_FRAME_START_DELAY(0);
+	val |= PIPECONF_FRAME_START_DELAY(3);
 
 	I915_WRITE(PIPECONF(pipe), val);
 	POSTING_READ(PIPECONF(pipe));
@@ -16524,7 +16524,7 @@  static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = I915_READ(reg);
 		val &= ~HSW_FRAME_START_DELAY_MASK;
-		val |= HSW_FRAME_START_DELAY(0);
+		val |= HSW_FRAME_START_DELAY(3);
 		I915_WRITE(reg, val);
 	} else {
 		i915_reg_t reg = PIPECONF(cpu_transcoder);
@@ -16532,7 +16532,7 @@  static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = I915_READ(reg);
 		val &= ~PIPECONF_FRAME_START_DELAY_MASK;
-		val |= PIPECONF_FRAME_START_DELAY(0);
+		val |= PIPECONF_FRAME_START_DELAY(3);
 		I915_WRITE(reg, val);
 	}
 
@@ -16545,7 +16545,7 @@  static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = I915_READ(reg);
 		val &= ~TRANS_FRAME_START_DELAY_MASK;
-		val |= TRANS_FRAME_START_DELAY(0);
+		val |= TRANS_FRAME_START_DELAY(3);
 		I915_WRITE(reg, val);
 	} else {
 		i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
@@ -16553,7 +16553,7 @@  static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc
 
 		val = I915_READ(reg);
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
-		val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+		val |= TRANS_CHICKEN2_FRAME_START_DELAY(3);
 		I915_WRITE(reg, val);
 	}
 }