reset-mi-mode

Submitted by Chris Wilson on Sept. 10, 2019, 6:35 a.m.

Details

Message ID 20190910063535.29385-1-chris@chris-wilson.co.uk
State New
Headers show
Series "reset-mi-mode" ( rev: 1 ) in Intel GFX - Try Bot

Not browsing as part of any series.

Commit Message

Chris Wilson Sept. 10, 2019, 6:35 a.m.
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 37 +++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f073aea6a1fe..5ca35b20eaf7 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2368,6 +2368,42 @@  static struct i915_request *active_request(struct i915_request *rq)
 	return active;
 }
 
+static u32 *lrc_find_reg(u32 *lrc, u32 reg)
+{
+	u32 * const end = lrc + PAGE_SIZE / sizeof(*lrc);
+
+	while (lrc < end) {
+		u32 lri = *lrc++;
+
+		if (lri == 0)
+			continue;
+
+		if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0))
+			break;
+
+		lri &= 0x7f;
+		lri++;
+		do {
+			if (*lrc == reg)
+				return lrc + 1;
+		} while (lrc += 2, lri -= 2);
+	}
+
+	return NULL;
+}
+
+static void __execlists_reset_reg_state(const struct intel_context *ce,
+					const struct intel_engine_cs *engine)
+{
+	u32 *x;
+
+	x = lrc_find_reg(ce->lrc_reg_state, engine->mmio_base + 0x9c);
+	if (x) {
+		pr_info("0x9c = %ld\n", x - ce->lrc_reg_state);
+		*x |= _MASKED_BIT_DISABLE(STOP_RING);
+	}
+}
+
 static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
 {
 	struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -2455,6 +2491,7 @@  static void __execlists_reset(struct intel_engine_cs *engine, bool stalled)
 	GEM_TRACE("%s replay {head:%04x, tail:%04x\n",
 		  engine->name, ce->ring->head, ce->ring->tail);
 	intel_ring_update_space(ce->ring);
+	__execlists_reset_reg_state(ce, engine);
 	__execlists_update_reg_state(ce, engine);
 	mutex_release(&ce->pin_mutex.dep_map, 0, _THIS_IP_);