radeon/vcn: add RENOIR VCN decode support

Submitted by Zhang, Boyuan on Sept. 4, 2019, 5:49 p.m.

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Message ID BL0PR12MB252932DE0B3867534A9462BB87B80@BL0PR12MB2529.namprd12.prod.outlook.com
State New
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Series "radeon/vcn: add RENOIR VCN decode support" ( rev: 2 ) in Mesa

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Commit Message

Zhang, Boyuan Sept. 4, 2019, 5:49 p.m.
Patch is
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>


-----Original Message-----
From: mesa-dev <mesa-dev-bounces@lists.freedesktop.org> On Behalf Of Liu, Leo

Sent: September 4, 2019 1:40 PM
To: mesa-dev@lists.freedesktop.org
Subject: [Mesa-dev] [PATCH] radeon/vcn: add RENOIR VCN decode support

It has same VCN2.x block as Navi1x

Signed-off-by: Leo Liu <leo.liu@amd.com>

---
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.17.1

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diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 77bfe187674..0743d47f703 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -840,7 +840,7 @@  static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
 	decode->sc_coeff_size = 0;
 
 	decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
-	decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS &&
+	decode->db_pitch = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR &&
 			dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9) ?
 			align(dec->base.width, 64) :
 			align(dec->base.width, 32) ;
@@ -938,7 +938,7 @@  static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
 			/* default probability + probability data */
 			ctx_size = 2304 * 5;
 
-			if (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS) {
+			if (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) {
 				/* SRE collocated context data */
 				ctx_size += 32 * 2 * 128 * 68;
 				/* SMP collocated context data */
@@ -1263,7 +1263,7 @@  static unsigned calc_dpb_size(struct radeon_decoder *dec)
 	case PIPE_VIDEO_FORMAT_VP9:
 		max_references = MAX2(max_references, 9);
 
-		dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_ARCTURUS) ?
+		dpb_size = (((struct si_screen*)dec->screen)->info.family >= CHIP_RENOIR) ?
 			(8192 * 4320 * 3 / 2) * max_references :
 			(4096 * 3000 * 3 / 2) * max_references;
 
@@ -1607,7 +1607,7 @@  struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
 		dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
 		dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
 		dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
-	} else if (sctx->family >= CHIP_NAVI10) {
+	} else if (sctx->family >= CHIP_NAVI10 || sctx->family == CHIP_RENOIR) {
 		dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
 		dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
 		dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;