[v4,5/7] drm/i915: Add new GMP register size for GEN11

Submitted by Mun, Gwan-gyeong on Sept. 3, 2019, 9:12 a.m.

Details

Message ID 20190903091235.32304-6-gwan-gyeong.mun@intel.com
State New
Headers show
Series "drm/i915/dp: Support for DP HDR outputs" ( rev: 4 ) in Intel GFX

Not browsing as part of any series.

Commit Message

Mun, Gwan-gyeong Sept. 3, 2019, 9:12 a.m.
According to Bspec, GEN11 and prior GEN11 have different register size for
HDR Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for
GEN11. And it makes handle different register size for
HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN
platforms. It addresses Uma's review comments.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++--
 drivers/gpu/drm/i915/i915_reg.h           |  1 +
 2 files changed, 9 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c500fc9154c8..287999b31217 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -189,13 +189,19 @@  hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 	}
 }
 
-static int hsw_dip_data_size(unsigned int type)
+static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
+			     unsigned int type)
 {
 	switch (type) {
 	case DP_SDP_VSC:
 		return VIDEO_DIP_VSC_DATA_SIZE;
 	case DP_SDP_PPS:
 		return VIDEO_DIP_PPS_DATA_SIZE;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		if (INTEL_GEN(dev_priv) >= 11)
+			return VIDEO_DIP_GMP_DATA_SIZE;
+		else
+			return VIDEO_DIP_DATA_SIZE;
 	default:
 		return VIDEO_DIP_DATA_SIZE;
 	}
@@ -514,7 +520,7 @@  static void hsw_write_infoframe(struct intel_encoder *encoder,
 	int i;
 	u32 val = I915_READ(ctl_reg);
 
-	data_size = hsw_dip_data_size(type);
+	data_size = hsw_dip_data_size(dev_priv, type);
 
 	val &= ~hsw_infoframe_enable(type);
 	I915_WRITE(ctl_reg, val);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c43b8c583bb..8b31ad7426d6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4667,6 +4667,7 @@  enum {
  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE	32
+#define   VIDEO_DIP_GMP_DATA_SIZE	36
 #define   VIDEO_DIP_VSC_DATA_SIZE	36
 #define   VIDEO_DIP_PPS_DATA_SIZE	132
 #define VIDEO_DIP_CTL		_MMIO(0x61170)

Comments

>-----Original Message-----

>From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Gwan-

>gyeong Mun

>Sent: Tuesday, September 3, 2019 2:43 PM

>To: intel-gfx@lists.freedesktop.org

>Cc: Shankar, Uma <uma.shankar@intel.com>; dri-devel@lists.freedesktop.org

>Subject: [PATCH v4 5/7] drm/i915: Add new GMP register size for GEN11

>

>According to Bspec, GEN11 and prior GEN11 have different register size for HDR

>Metadata Infoframe SDP packet. It adds new VIDEO_DIP_GMP_DATA_SIZE for

>GEN11. And it makes handle different register size for

>HDMI_PACKET_TYPE_GAMUT_METADATA on hsw_dip_data_size() for each GEN

>platforms. It addresses Uma's review comments.


Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>


>Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

>---

> drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++--

> drivers/gpu/drm/i915/i915_reg.h           |  1 +

> 2 files changed, 9 insertions(+), 2 deletions(-)

>

>diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c

>b/drivers/gpu/drm/i915/display/intel_hdmi.c

>index c500fc9154c8..287999b31217 100644

>--- a/drivers/gpu/drm/i915/display/intel_hdmi.c

>+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c

>@@ -189,13 +189,19 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,

> 	}

> }

>

>-static int hsw_dip_data_size(unsigned int type)

>+static int hsw_dip_data_size(struct drm_i915_private *dev_priv,

>+			     unsigned int type)

> {

> 	switch (type) {

> 	case DP_SDP_VSC:

> 		return VIDEO_DIP_VSC_DATA_SIZE;

> 	case DP_SDP_PPS:

> 		return VIDEO_DIP_PPS_DATA_SIZE;

>+	case HDMI_PACKET_TYPE_GAMUT_METADATA:

>+		if (INTEL_GEN(dev_priv) >= 11)

>+			return VIDEO_DIP_GMP_DATA_SIZE;

>+		else

>+			return VIDEO_DIP_DATA_SIZE;

> 	default:

> 		return VIDEO_DIP_DATA_SIZE;

> 	}

>@@ -514,7 +520,7 @@ static void hsw_write_infoframe(struct intel_encoder

>*encoder,

> 	int i;

> 	u32 val = I915_READ(ctl_reg);

>

>-	data_size = hsw_dip_data_size(type);

>+	data_size = hsw_dip_data_size(dev_priv, type);

>

> 	val &= ~hsw_infoframe_enable(type);

> 	I915_WRITE(ctl_reg, val);

>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

>6c43b8c583bb..8b31ad7426d6 100644

>--- a/drivers/gpu/drm/i915/i915_reg.h

>+++ b/drivers/gpu/drm/i915/i915_reg.h

>@@ -4667,6 +4667,7 @@ enum {

>  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte

>  * of the infoframe structure specified by CEA-861. */

> #define   VIDEO_DIP_DATA_SIZE	32

>+#define   VIDEO_DIP_GMP_DATA_SIZE	36

> #define   VIDEO_DIP_VSC_DATA_SIZE	36

> #define   VIDEO_DIP_PPS_DATA_SIZE	132

> #define VIDEO_DIP_CTL		_MMIO(0x61170)

>--

>2.23.0

>

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