[07/10] drm/amdgpu: init UMC & RSMU register base address

Submitted by Hawking Zhang on Sept. 3, 2019, 12:02 a.m.

Details

Message ID 1567468894-11852-7-git-send-email-Hawking.Zhang@amd.com
State Accepted
Commit 9dc913425807c82a7cb942458540a9423182697d
Headers show
Series "Series without cover letter" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Hawking Zhang Sept. 3, 2019, 12:02 a.m.
UMC RAS feature requires access to UMC & RSMU registers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c | 2 ++
 1 file changed, 2 insertions(+)

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diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
index 4853899..e62609d 100644
--- a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
@@ -52,6 +52,8 @@  int arct_reg_base_init(struct amdgpu_device *adev)
 		adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));
 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
+		adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));
 	}
 	return 0;
 }