[04/15] drm/i915/dsb: Added enum for reg write capability.

Submitted by Animesh Manna on Aug. 20, 2019, 4:50 a.m.

Details

Message ID 20190820045020.7510-4-animesh.manna@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX - Try Bot

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Commit Message

Animesh Manna Aug. 20, 2019, 4:50 a.m.
DSB can access specific register, To identify those register
which can be written through DSB, enum reg_write_cap is added
to hold the capability.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea2f0fa2402d..4ca7c0f2e734 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,11 +178,22 @@ 
  */
 #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
 
+/*
+ * Added enum to hold the capability for those registers which can be written
+ * through DSB.
+ */
+enum reg_write_cap {
+	MMIO_WRITE,
+	DSB_WRITE,
+	DSB_INDEX_WRITE
+};
+
 typedef struct {
 	u32 reg;
+	enum reg_write_cap cap;
 } i915_reg_t;
 
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__})
 
 #define INVALID_MMIO_REG _MMIO(0)