[v2,37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression

Submitted by Lucas De Marchi on Aug. 17, 2019, 9:38 a.m.

Details

Message ID 20190817093902.2171-38-lucas.demarchi@intel.com
State New
Headers show
Series "Tiger Lake batch 3" ( rev: 4 3 2 ) in Intel GFX

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Commit Message

Lucas De Marchi Aug. 17, 2019, 9:38 a.m.
From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

Patch hide | download patch | download mbox

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..fb7270bf9670 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,16 @@  extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear and
+ * at index 1. A CCS cache line corresponds to an area of 4x1 tiles in the main
+ * surface. The main surface pitch is required to be a multiple of 4 tile
+ * widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *

Comments

On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> 

> Gen-12 has a new compression format, add a new modifier for userspace

> to

> indicate that.

> 

> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

> Cc: Daniel Vetter <daniel.vetter@intel.com>

> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

> ---

>  include/uapi/drm/drm_fourcc.h | 10 ++++++++++

>  1 file changed, 10 insertions(+)

> 

> diff --git a/include/uapi/drm/drm_fourcc.h

> b/include/uapi/drm/drm_fourcc.h

> index 3feeaa3f987a..fb7270bf9670 100644

> --- a/include/uapi/drm/drm_fourcc.h

> +++ b/include/uapi/drm/drm_fourcc.h

> @@ -410,6 +410,16 @@ extern "C" {

>  #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)

>  #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)

>  

> +/*

> + * Intel color control surfaces (CCS) for Gen-12 render compression.

> + *

> + * The main surface is Y-tiled and is at plane index 0 whereas CCS

> is linear and

> + * at index 1. A CCS cache line corresponds to an area of 4x1 tiles

> in the main

> + * surface. The main surface pitch is required to be a multiple of 4

> tile

> + * widths.

> + */

> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL,

> 6)

> +

>  /*

>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized

> macroblocks

>   *


Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>